Clock and data recovery circuit

A clock and data recovery circuit comprising:

• a circuit which generates 2N-phase clock signals with phases thereof being equally spaced by 180/N degrees;
• N interpolators, each of which receives from among the 2N-phase clock signals two of the clock signals with phases thereof separated by 360/N degrees, performs phase interpolation, and generates a signal obtained by the interpolation and a signal having a phase reverse to a phase of the signal obtained by the interpolation;
• said N interpolators providing 2N-phase clock signals with phases thereof interpolated;
• and
• a 2N-phase to 4N-phase conversion circuit which buffers the 2N-phase clock signals from said N interpolators and delivers the buffered 2N-phase clock signals without alteration, and generates 2N-phase clock signals each having a phase intermediate between the mutually adjacent phases of two of the 2N-phase clock signals from said N interpolators, thereby providing a total of 4N-phase clock signals;
• a set of the 2N-phase clock signals among the 4N-phase signals from said 2N-phase 4N-phase conversion circuit being used for input data detection and the remaining 2N-phase clock signals being used for edge detection.

A clock and data recovery circuit comprising:

• a four-phase clock generation circuit which generates clock signals of four phases equally spaced by 90 degrees;
• a first interpolator which receives the clock signals with first and third phases of the four phases, performs phase interpolation, and generates a signal obtained by the interpolation and a signal with a phase reverse to a phase of the signal obtained by the interpolation;
• a second interpolator which receives the clock signals with second and fourth phases of the four phases, performs phase interpolation, and generates a signal obtained by the interpolation and a signal with a phase reverse to a phase of the signal obtained by the interpolation;
• and
• a four phase-to eight-phase conversion circuit which receives the four-phase clock signals from said first and second interpolators, buffers the four-phase clock signals from said first and second interpolators and delivers the buffered four-phase clock signals without alteration, and generates four-phase clock signals obtained by interpolating two of the clock signals having the mutually adjacent phases among the four-phase clock signals output from said first and second interpolators, thereby providing eight-phase clock signals;
• a set of the four-phase clock signals among the eight-phase clock signals from said four-phase to eight-phase conversion circuit being used for data detection of serial data and the remaining four-phase clock signals being used for edge detection of the serial data, the serial data having even data and odd data multiplexed therein, for transfer.