Signal Transfer Across Circuits Operating in Different Clock Domains
AssigneeTexas Instruments Incorporated
InventorJignesh PAWAR
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Abstract
Signal transfer across circuits operating in different clock domains. According to an aspect of the present invention, a freeze signal is generated when it is determined that data is to be transferred from a first clocked element to a second clocked element. The freeze signal thus generated causes the first clocked element to stop updating the corresponding data so that such the data value remains static for some duration. Due to such stopping, signal value (i.e., data) may be reliably transferred to the second clocked element.
Claims17
A method of synchronizing transfer of data signals from a first element to a second element, said first element being clocked by a first clock signal and said second element being clocked by a second clock signal, said first clock signal and said second clock signal respectively operating in a first clock domain and a second clock domain, wherein said first clock domain is not identical to said second clock domain, said method comprising:
- determining when to initiate transfer of a data signal present at said first element to said second element;
- sending to said first element a freeze signal upon said determining;
- freezing said data signal in said first element for at least a finite duration in response to reception of said freeze signals such that said data signal does not change during said finite duration;
- and
- reading said data signal from said first element in said finite duration.
A signal transfer circuit transferring data signals from a first element to a second element, said first element being clocked by a first clock signal and said second element being clocked by a second clock signal, said first clock signal and said second clock signal respectively operating in a first clock domain and a second clock domain, wherein said first clock domain is not identical to said second clock domain, said signal transfer circuit comprising:
- a synchronizer sending a freeze signal;
- a freeze circuit freezing a data signal in said first element for at least a finite duration in response to reception of said freeze signal such that said data signal does not change in said first element during said finite duration;
- and
- a read circuit reading said data signal from said first element in said finite duration.
An article of manufacture for synchronizing transfer of data signals from a first element to a second element, said first element being clocked by a first clock signal and said second element being clocked by a second clock signal, said first clock signal and said second clock signal respectively operating in a first clock domain and a second clock domain, wherein said first clock domain is not identical to said second clock domain, said article comprising:
- means for determining when to initiate transfer of a data signal present at said first element to said second element;
- means for sending to said first element a freeze signal upon said determining;
- means for freezing said data signal in said first element for at least a finite duration in response to reception of said freeze signals such that said data signal does not change during said finite duration;
- and
- means for reading said data signal from said first element in said finite duration.
Dependencies are inferred from the claim text.