Receiver having dc offset voltage correction

Abstract

A receiver comprises a frequency down-conversion stage (14) for demodulating a received signal to produce an uncorrected demodulated signal (vin ), a dc offset voltage correcting circuit (22) having an output (28) for a corrected signal and a data recovery circuit (42) coupled to the output. The dc offset voltage correcting circuit (22) comprises an input for the uncorrected demodulated signal (vin), a bit slicer (30) for detecting received data, a filter (32) coupled to the output of the bit slicer for regenerating the demodulated signal less noise and dc offset, a subtracting stage (34) for subtracting the regenerated demodulated signal from a delayed version of the uncorrected demodulated signal to produce the dc offset voltage (voff) and a feedback circuit for feeding back the dc offset voltage to the bit slicer.

Dependencies are inferred from the claim text.