Processors for network communications
AssigneeFujitsu Semiconductor Limited
InventorsKartik Raju, Mehmet Un
Life of this patent
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Abstract
Disclosed are processors for implementing the Media-access control layer of a network device.
Claims38
A processor unit comprising:
- A main processor having a data path having an instruction fetcher, a regular instruction decoder, internal registers, at least one operand bus, an address bus, an output bus, and an extension-instruction decoder;
- a set of extension registers accessible to the main processor by the address lines and at least the output bus;
- and
- a coprocessor, responsive to a signal from the extension-instruction decoder, that is adapted to use signals on the at least one operand bus, the coprocessor further adapted to obtain data from one or more of the extension registers.
A processor unit comprising:
- A main processor having a data path having an instruction fetcher, a regular instruction decoder, internal registers, at least one operand bus, an address bus, an output bus, and an extension-instruction decoder;
- a set of extension registers accessible to the main processor by the address lines and the at least one operand bus;
- and
- a coprocessor, responsive to a signal from the extension-instruction decoder, that is adapted to use signals on the at least one operand bus, the coprocessor further adapted to store result data in one or more of the extension registers.
A processor unit comprising:
- a main processor having a data path having a regular instruction decoder, internal registers, at least one operand bus, an address bus, an output bus, and an extension-instruction decoder, an extension instruction being a custom instruction for a special purpose, the extension-instruction decoder adapted to detect the presence of an extension instruction on the processor's data path and to generate a corresponding signal;
- and
- a coprocessor, responsive to a signal from the extension-instruction decoder, that is adapted to interpret signals on the at least one operand bus for the identity of a task to be performed.
The processor unit of claim 18 wherein the coprocessor is further adapted to receive a configuration parameter on the at least one operand bus, the configuration parameter setting a corresponding aspect of the coprocessor's operation.
A media-access control processor for exchanging data with a physical-layer control unit, the physical-layer control unit interfacing with a communications medium, the media-access control processor comprising:
- a first output port to provide data to the physical-layer control unit;
- a first input port to receive data from the physical-layer control unit;
- a main processor adapted to provide data to the output port and to receive data from the input port;
- a CRC coprocessor adapted to generate a cyclic-redundancy-check from an input set of data bytes, the CRC coprocessor having an input to receive an input set of data bytes from the main processor and an output to provide a header-check sequence for the input set of data bytes to the main processor;
- an HCS coprocessor adapted to generate a header-check sequences from an input header, the HCS coprocessor having an input to receive a plurality of bytes of a header from the main processor and an output to provide a header-check sequence therefor to the main processor;
- an DES coprocessor adapted to generate an output set of data bytes processed according to the Data Encryption Standard from an input set of data bytes, the processing being one of the encryption process and the decryption process according to the standard, the DES coprocessor having an input to receive an input set of data bytes from the main processor and an output to provide a set of processed data bytes to the main processor;
- and
- an CCM coprocessor adapted to generate an output set of data bytes processed according to the counter with cipher block chaining messaging authentication code (CCM) protocol standard from an input set of data bytes, the processing being one of the encryption process and the decryption process according to the standard, the CCM coprocessor having an input to receive an input set of data bytes from the main processor and an output to provide a set of processed data bytes to the main processor.
A media-access control processor for exchanging data with a physical-layer control unit, the physical-layer control unit interfacing with a communications medium, the media-access control processor comprising:
- a first output port to provide data to the physical-layer control unit;
- a first input port to receive data from the physical-layer control unit;
- a main processor adapted to provide data to the output port and to receive data from the input port;
- a CRC coprocessor adapted to generate a cyclic-redundancy-check from an input set of data bytes, the CRC coprocessor having an input to receive an input set of data bytes from the main processor and an output to provide a header-check sequence for the input set of data bytes to the main processor;
- and
- an HCS coprocessor adapted to generate a header-check sequences from an input header, the HCS coprocessor having an input to receive a plurality of bytes of a header from the main processor and an output to provide a header-check sequence therefor to the main processor.
A media-access control processor for exchanging data with a physical-layer control unit, the physical-layer control unit interfacing with a communications medium, the media-access control processor comprising:
- a first output port to provide data to the physical-layer control unit;
- a first input port to receive data from the physical-layer control unit;
- a main processor adapted to provide data to the output port and to receive data from the input port;
- a coprocessor adapted to generate one of a cyclic-redundancy-check value or a header-check sequence from an input set of data bytes, the coprocessor having an input to receive an input set of data bytes from the main processor and an output to provide the one of a cyclic-redundancy-check value or the or a header-check sequence to the main processor;
- and
- an cipher coprocessor adapted to generate an output set of data bytes processed according to a ciphering standard, the processing being one of the encryption and decryption process according to the ciphering standard, the cipher coprocessor having an input to receive an input set of data bytes from the main processor and an output to provide a set of processed data bytes to the main processor.
A method of directing the operation of a control processor having a main processor and a coprocessor, the main processor having a data path having an instruction fetcher, a regular instruction decoder, internal registers, at least one operand bus, an address bus, an output bus, and an extension-instruction decoder, a set of extension registers accessible to the main processor by the address bus and at least the output bus, and further accessible to the coprocessor, the method comprising the steps of:
- directing the main processor to load the extension registers with data for an extension instruction through its normal data path operations;
- and
- thereafter outputting an extension instruction to be decoded by the extension-instruction decoder and thereafter conveyed to the coprocessor.
A method of directing the operation of a control processor having a main processor and a coprocessor, the main processor having a data path having an instruction fetcher, a regular instruction decoder, internal registers, at least one operand bus, an address bus, an output bus, and an extension-instruction decoder, a set of extension registers accessible to the main processor by the address lines and at least the output bus, and further accessible to the coprocessor, the method comprising the steps of:
- outputting an extension instruction to be decoded by the extension-instruction decoder and thereafter conveyed to the coprocessor;
- and
- thereafter directing the main processor to read data from the extension registers through its normal data path operations, the data being placed there by the coprocessor through a connection that is different from the main processor's data path.
A method of a main processor directing the operation of a coprocessor comprising the step of providing a signal to the coprocessor to direct the coprocessor to input signals from an operand bus, and of providing signals on the operand bus that direct the coprocessor to perform a specific task.
Dependencies are inferred from the claim text.