Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorTakashi OHSAWA
Life of this patent
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Abstract
This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second dummy word lines connected to gates of the first and the second dummy cells; a pair of bit lines; and a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as a reference or detecting the second data using the first data as a reference in a refresh operation of the first and the second dummy cells
Claims16
A semiconductor memory device comprising:
- memory cells including floating bodies in an electrically floating state and storing data based on the number of majority carriers within the floating bodies;
- a first dummy cell and a second dummy cell generating a reference data which becomes a data detection reference at the time of detecting the data of the memory cells and storing first data and second data of mutually opposite polarities, respectively;
- word lines connected to gates of the memory cells;
- a first dummy word line and a second dummy word line connected to a gate of the first dummy cell and a gate of the second dummy cell, respectively;
- a pair of bit lines connected to sources or drains of the memory cells;
- and
- a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as the reference data or detecting the second data using the first data as the reference data in a refresh operation of the first and the second dummy cells, the refresh operation being an operation in which data stored in the first or the second dummy cell is read, then the data is written back to the same dummy cell.
A semiconductor memory device comprising:
- memory cells including floating bodies in an electrically floating state and storing data based on the number of majority carriers within the floating bodies;
- a first dummy cell and a second dummy cell generating a reference current which becomes a data detection reference at the time of detecting the data of the memory cells and storing first data and second data of mutually opposite polarities, respectively;
- word lines connected to gates of the memory cells;
- a first dummy word line and a second dummy word line connected to a gate of the first dummy cell and a gate of the second dummy cell, respectively;
- a pair of bit lines connected to sources or drains of the memory cells;
- a first sense amplifier provided for the pair of bit lines and sensing data of one of the memory cells;
- a pair of sense nodes provided within the first sense amplifier;
- and
- two transfer gates provided between the pair of sense nodes and the pair of bit lines and controlled by different signals, wherein
- at the time of writing the first and the second data into the first and the second dummy cells or at the time of a refresh operation of the first and the second dummy cells, one of the two transfer gates becomes off and the other transfer gate becomes on, for setting potentials of the pair of sense nodes asymmetrical, and the first sense amplifier simultaneously writes the first data and the second data into the first dummy cell and the second dummy cell, respectively, using a difference between potentials of the pair of sense nodes.
Dependencies are inferred from the claim text.