Low voltage data path and current sense amplifier

A data path coupled to a read/write circuit, comprising:

• a local input/output (LIO) line having first and second signal lines coupled to the read/write circuit;
• a global input/output (GIO) line having first and second signal lines;
• and
• a source follower circuit, wherein the source follower circuit includes:
• first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO respectively, a gate coupled to the first and the second signal lines of the LIO respectively;
• third and fourth NMOS transistors having a source coupled to a source of the first and the second NMOS transistors respectively, a gate coupled to a reference voltage supply, and a drain coupled together;
• and
• a fifth NMOS transistor having a drain coupled to the drain of the third and fourth NMOS transistors, a gate to which a selection signal is applied, and a source coupled to a ground.

A data path coupled to a read/write circuit, comprising:

• a local input/output (LIO) line having first and second signal lines coupled to the read/write circuit;
• a global input/output (GIO) line having first and second signal lines;
• and
• a source follower circuit, wherein the source follower circuit includes:
• first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO respectively, a gate coupled to the first and the second signal lines of the LIO respectively;
• third and fourth NMOS transistors having a source coupled to a source of the first and the second NMOS transistors respectively, a gate coupled to a reference voltage supply, and a drain coupled together;
• a fifth NMOS transistor having a drain coupled to the drain of the third and fourth NMOS transistors, a gate to which a selection signal is applied, and a source coupled to a ground;
• and
• a sixth NMOS transistor having a drain coupled to a source region of the first NMOS transistor, a source coupled to a source region of the second NMOS transistor and a gate to which an equilibrate signal is applied.

A current sense amplifier, comprising:

• first and second load circuits, each load circuit having a first terminal coupled to a peripheral voltage supply and further having a second terminal;
• first and second NMOS transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit and further coupled to an output buffer to provide complementary output voltage signals, a gate coupled to the drain of the other NMOS transistor, and a source coupled to first and second lines of a GIO line;
• a precharge circuit coupled to the source of the first and the second NMOS transistors;
• and
• wherein the first and the second lines of the GIO are coupled to a source follower circuit.

A data path coupled to a read/write circuit, comprising:

• a local input/output (LIO) line having first and second signal lines coupled to the read/write circuit;
• a global input/output (GIO) line having first and second signal lines;
• a source follower circuit, wherein the source follower circuit includes:
• first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO respectively, a gate coupled to the first and the second signal lines of the LIO respectively, and a source coupled together;
• a third NMOS transistor having a source coupled to the source of the first and the second NMOS transistors and a gate coupled to a reference voltage supply;
• and
• a fourth NMOS transistor having a drain coupled to a drain of the third NMOS transistor, a gate to which a selection signal is applied, and a source coupled to a ground;
• and
• a current sense amplifier, wherein the current sense amplifier includes:
• first and second load circuits, each load circuit having a first terminal coupled to a peripheral voltage supply and further having a second terminal;
• first and second NMOS transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit and further coupled to an output buffer to provide complementary output voltage signals, a gate coupled to the drain of the other NMOS transistor, and a source coupled to the first and second lines of the GIO;
• and
• a precharge circuit coupled to the source of the first and the second NMOS transistors.

A memory device, comprising:

• an address bus;
• a control bus;
• an address decoder coupled to the address bus;
• a control circuit coupled to the control bus;
• a memory cell array coupled to the address decoder and the control circuit;
• a read/write circuit coupled to the memory cell array;
• and
• a data path coupled to a read/write circuit, wherein the data path includes:
• a local input/output (LIO) line having first and second signal lines coupled to the read/write circuit;
• a global input/output (GIO) line having first and second signal lines;
• and
• a source follower circuit including:
• first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO respectively, a gate coupled to the first and the second signal lines of the LIO respectively, and a source coupled together;
• a third NMOS transistor having a source coupled to the source of the first and the second NMOS transistors and a gate coupled to a reference voltage supply;
• and
• a fourth NMOS transistor having a drain coupled to a drain of the third NMOS transistor, a gate to which a selection signal is applied, and a source coupled to a ground.

A memory device, comprising:

• a memory array coupled to a read/write circuit;
• an output buffer;
• and
• a data path coupled between the read/write circuit and the output buffer, wherein the data path includes:
• a local input/output (LIO) line and a global input/output (GIO) line coupled by a source follower circuit, first and second signal lines of LIO line coupled to the read/write circuit and first and second signal lines of the GIO coupled to a current sense amplifier, the current sense amplifier coupled to the output buffer;
• and
• wherein the source follower circuit includes:
• first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO respectively and a gate coupled to the first and the second signal lines of the LIO respectively;
• a third NMOS transistor having a source coupled to a source of the first and the second NMOS transistors and a gate coupled to a reference voltage supply;
• and
• a fourth NMOS transistor having a drain coupled to a drain of the third NMOS transistor, a gate to which a selection signal is applied, and a source coupled to a ground.

A processor based system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, wherein the memory device includes a data path coupled between a read/write circuit of a memory array and an output buffer, wherein the data path includes a local input/output (LIO) line and a global input/output (GIO) line coupled by a source follower circuit, first and second signal lines of LIO line coupled to the read/write circuit and first and second signal lines of the GIO coupled to a current sense amplifier, the current sense amplifier coupled to the output buffer, wherein the source follower circuit includes:
• first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO respectively and a gate coupled to the first and the second signal lines of the LIO respectively;
• a third NMOS transistor having a source coupled to a source of the first and the second NMOS transistors and a gate coupled to a reference voltage supply;
• and
• a fourth NMOS transistor having a drain coupled to a drain of the third NMOS transistor, a gate to which a selection signal is applied, and a source coupled to a ground.

A method of coupling data from a read/write circuit to an output buffer, comprising:

• coupling first and the second signal lines of a GIO to a drain of first and second n-channel MOS (NMOS) transistors, respectively, in a source follower circuit;
• coupling first and the second signal lines of a LIO to a gate of the first and second NMOS transistors respectively, the first and second signal lines of the LIO coupled to the read/write circuit;
• coupling a reference voltage supply to a gate of a third NMOS transistor in the source follower circuit, the third NMOS transistor having a source coupled to a source of the first and the second NMOS transistors;
• coupling a drain of a fourth NMOS transistor in the source follower circuit to a drain of the third NMOS transistor, the fourth NMOS transistor having a source coupled to a ground;
• and
• coupling a gate of the fourth NMOS transistor to a selection signal.

A method of forming a data path for a read/write circuit, comprising:

• forming a source follower circuit in a center logic portion of a dynamic random access memory (DRAM) array, wherein forming the source follower circuit includes:
• forming a first and a second n-channel MOS (NMOS) transistor having a source coupled together;
• forming a third NMOS transistor having a source coupled to the source of the first and the second NMOS transistors and a gate coupled to a reference voltage supply;
• and
• forming a fourth NMOS transistor having a drain coupled to a drain of the third NMOS transistor, a gate coupled to a selection signal line, and a source coupled to a ground;
• forming a local input/output (LIO) line to have first and second signal lines coupled to a read/write circuit and to a gate of first and second NMOS transistors respectively;
• and
• forming a global input/output (GIO) line to have first and second signal lines coupled to a drain of the first and second NMOS transistors respectively.

A method of forming a data path for a read/write circuit, comprising:

• forming a local input/output (LIO) line having first and second signal lines coupled to the read/write circuit;
• forming a global input/output (GIO) line having first and second signal lines coupled to a current sense amplifier;
• and
• forming a source follower circuit to connect the first and second signal lines of the GIO to the first and second signal lines of the LIO such that a current flows from the current sense amplifier to the source follower circuit during a read operation.