Three-level nonvolatile semiconductor memory device and associated method of operation

A method of operating a nonvolatile semiconductor memory device comprising a memory array including first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines, wherein the first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations, the method comprising:

• primarily controlling threshold voltages of first and second memory cells based on first and second bits;
• and,
• after primarily controlling the threshold voltages of the first and second memory cells, secondarily controlling the threshold voltages of the first and second memory cells based on a third bit;
• wherein the first and second memory cells are connected to the same word line and are arranged in the first and second even strings, respectively, or in the first and second odd strings, respectively.

A method of operating a nonvolatile semiconductor memory device comprising a memory array including first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines, wherein the first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations, the method comprising:

• (a) detecting the levels of threshold voltages of first and second memory cells relative to a second reference voltage through respective first and second common bit lines;
• (b) switching first and second latch data based on respective voltage levels of the first and second common bit lines during (a);
• (c) reflecting the level of the threshold voltage of the first or second memory cell relative to a first reference voltage and a voltage level of the first latch data, on the second common bit line;
• and,
• (d) switching the second latch data based on the voltage level of the second common bit line during (c);
• wherein the first and second memory cells are controlled by the same word line and are arranged in the first and second even strings, respectively, or in the first and second odd strings, respectively.

A method of operating a nonvolatile semiconductor memory device comprising a memory array including first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines, wherein the first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations, the method comprising:

• (a) detecting the levels of threshold voltages of first and second memory cells relative to a predetermined reference voltage through respective first and second common bit lines;
• (b) switching first and second latch data depending on respective voltage levels of the first and second common bit lines obtained by (a);
• (c) reflecting a voltage level of the first latch data on the second common bit line;
• and,
• (d) switching the second latch data depending on a voltage level of the second common bit line obtained by (c);
• wherein the first and second memory cells are controlled by the same word line and are arranged in the first and second even strings, respectively, or in the first and second odd strings, respectively.