Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a memory cell array having a plurality of block each including a plurality of pages;
• a first non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array;
• a second non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell;
• a third non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell;
• a fourth non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array to be adjacent to the second non-volatile semiconductor memory cell;
• a first bit line extending along a bit line direction;
• a second bit line extending along the bit line direction;
• a first word line extending along a word line direction crossing the bit line direction, the electric charge storage layer of the first non-volatile semiconductor memory cell being capacity-coupled with the first word line, one end of a current path of the first non-volatile semiconductor memory cell being connected with one end of a current path of the third non-volatile semiconductor memory cell, the electric charge storage layer of the second non-volatile semiconductor memory cell being capacity-coupled with the first word line, one end of a current path of the second non-volatile semiconductor memory cell being connected with one end of a current path of the fourth non-volatile semiconductor memory cell;
• and
• a second word line extending along the word line direction, the electric charge storage layer of the third non-volatile semiconductor memory cell being capacity-coupled with the second word line, the other end of the current path of the third non-volatile semiconductor memory cell being electrically connected with the first bit line, the electric charge storage layer of the fourth non-volatile semiconductor memory cell being capacity-coupled with the second word line, the other end of the current path of the fourth non-volatile semiconductor memory cell being electrically connected with the second bit line,
• wherein regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell,
• regular data writing is performed with respect to the third non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell, and
• additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the third non-volatile semiconductor memory cell.