Flash memory device having bit lines decoded in irregular sequence
AssigneeSamsung Electronics Co., Ltd.
InventorJi-Ho CHO
Life of this patent
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Abstract
An embodiment of a flash memory device comprises a cell array including memory cells coupled to bit lines, a decoder configured to decode successive logical column addresses into physical column addresses that are arranged non-sequentially, and a gate circuit to partially select the bit lines in response to the decoded addresses. Physically adjacent bit lines may be activated so that electrical coupling effects are eliminated by non-successively activating the bit lines.
Claims19
A flash memory device comprising:
- a cell array including pluralities of memory cells coupled to pluralities of bit lines;
- a decoder configured to decode logically successive column addresses into physically discontinuous column addresses;
- and
- a gate circuit to partially select the bit lines in response to the decoded column addresses from the decoder.
A method of accessing cells in a flash memory device having bit lines coupled to the cells, the method comprising:
- generating selection signals in response to column addresses;
- and
- selecting the bit lines in response to the selection signals;
- wherein the selection signals are generated by decoding logically adjacent column addresses to select bit lines that are not physically adjacent.
A flash memory device having a burst read mode wherein data is continuously read in response to addresses generated internally in sequence, the memory device comprising:
- a memory cell array having memory cells coupled to local bit lines;
- a gate circuit to couple the local bit lines to sense amplifiers in response to selection signals;
- and
- a column decoder to generate the selection signals in response to column addresses by decoding logically sequential column addresses into physical column addresses in an irregular sequence.
Dependencies are inferred from the claim text.