Capacitor boost sensing

A memory cell connected to a bitline node for storing a memory state that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value during a read operation of the memory state, comprising:

• a parasitic bitline capacitance between the bitline node and ground;
• a first capacitor connected between a second node and ground;
• a first switch connected between the bitline node and the second node;
• a second switch and a third capacitor connected in series between the bitline node and the second node, with a terminal of the second switch being connected to the bitline node, the common connection node of the second switch and the third capacitor comprising a third node;
• and
• a third switch connected between the third node and ground,
• the first and third switches being adapted to be closed and the second switch to be open, in a first operation phase, and the first and third switches being adapted to be open and the second switch to be closed, in a second operation phase during which the cell voltage is boosted to the boost value.

A memory cell array, comprising a plurality of memory cells, each such memory cell for storing a memory state that gives rise to a cell voltage representing a bit value for that memory cell, each memory cell being capable of having the cell voltage increased to a boosted value during a read operation of the memory state and comprising:

• a first capacitor between a first node and ground;
• a second capacitor connected between a second node and ground;
• a first switch connected between the first node and the second node;
• a second switch and a third capacitor connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node;
• and
• a third switch connected between the third node and ground,
• the first and third switches being adapted to be closed and the second switch to be open, in a first operation phase, and the first and third switches being adapted to be open and the second switch to be closed, in a second operation phase during which the cell voltage is increased to the boosted value.

A method for increasing voltage at a node in a circuit comprising the steps of:

• providing a first node, a second node and a first switch connected between the first node and the second node;
• providing a second switch and a first capacitor connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the first capacitor comprising a third node;
• providing a third switch connected between the third node and ground;
• and
• in a first operation phase:
• closing the first and third switches and opening the second switch;
• and
• in a second operation phase:
• opening the first and third switches and closing the second switch, whereby, during the second operation phase, a voltage on the second node may be boosted to an amplified value.