Semiconductor integrated circuit device

Abstract

Source voltage and substrate voltage are supplied to a semiconductor integrated circuit 1E from the regulator circuits 11C and 21C of a power supply circuit 1C via a power detection compensating circuit 1D. The power efficiency value of a regulator is stored in the resistor 13D, various detection information and power values are input to an operator 14D, the power values and the power efficiency values of the regulator circuits 11C and 21C are accumulated, and the power sum of a semiconductor integrated circuit 1E and a power supply circuit 1C are output. Minimum power implementation information corresponding to the various detection information of the semiconductor integrated circuit 1E is stored in an LUT 15D. Variable resistances R1a and R2a are controlled for determining the reference voltage values of the regulator circuits 11C and 21C so that the power sum is the minimum power value by comparing the minimum power implementation information with the output of the operator 14D.

Dependencies are inferred from the claim text.