US 2007/0177057 A1Published application

Horizontal and vertical synchronization signal generating circuit

AssigneeSanyo Electric Co., Ltd.

InventorsTakemi Beppu, Naoyuki Konno

Life of this patent

Estimating the term…

Loading patent…

Abstract

Timing of internally generated horizontal synchronization signal and vertical synchronization signal is shifted. An internal clock is synchronized with a horizontal synchronization signal separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon. A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, a vertical synchronization signal is obtained in a VS output circuit 18. Here, the VS output circuit 18 internally has a delay circuit, and the timing of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS.

Claims3

Dependent claims

A horizontal and vertical synchronization signal generating circuit for generating a horizontal synchronization signal and a vertical synchronization signal, the circuit comprising:

a synchronization separation circuit for separating horizontal and vertical synchronization signals from a television signal;
a horizontal synchronization signal generating circuit for synchronizing an internal clock with the horizontal synchronization signal separated in the synchronization separation circuit to generate an internal horizontal synchronization signal based on the internal clock;
a normalizing circuit for normalizing timing of the vertical synchronization signal separated in the synchronization separation circuit based on the internal horizontal synchronization signal based on the internal clock;
and
a delay circuit for delaying, by a predetermined period of time, an internal vertical synchronization signal which is an output from the normalizing circuit, wherein
timing of the generated internal vertical synchronization signal against timing of the generated internal horizontal synchronization signal is shifted by a predetermined period of time.

3 more elements

Dependencies are inferred from the claim text.