Image sensor architecture employing one or more non-volatile memory cells

A monolithic image sensor formed in a substrate, said image sensor having a plurality of pixels, one or more of said plurality of pixels comprising:

• a memory device formed in said substrate, said memory device having a non-volatile memory cell, a control gate, a drain and a source;
• a photosensitive semiconductor device formed in said substrate and positioned for exposure to electromagnetic radiation from an image;
• a pixel control circuit formed in said substrate and connected to direct said memory device and said photosensitive semiconductor device to a plurality of controlled modes, said controlled modes including
• an erase mode in which at least a portion of an electric charge is removed from said non-volatile memory cell to place said memory device in an initialized state,
• an exposure mode in which said non-volatile memory cell is charged at least partially in response to a voltage at a terminal of said photosensitive semiconductor device, said voltage at said terminal corresponding to exposure of said photosensitive semiconductor device to said electromagnetic radiation from said image.

An image sensor, said image sensor having a plurality of pixels formed in a monolithic substrate, one or more of said plurality of pixels comprising:

• a memory device having a non-volatile memory cell, a control gate, a drain and a source;
• a photodiode positioned for exposure to electromagnetic radiation from an image;
• a FET transistor having a control gate, a drain connected to said cathode of said photodiode, and a source connected to said anode of said photodiode, said source of said FET transistor and said anode of said photodiode being further connected to said control gate of said memory device;
• a diode having an anode connected to said control gate of said memory device.

A digital camera comprising:

• an image sensor having an array of pixels, one or more of said pixels including
• a memory device having one of a floating gate, Ferro-magnetic gate or a Ferro-electric gate, a control gate, a drain and a source,
• a photosensitive semiconductor device positioned for exposure to electromagnetic radiation from an image,
• a pixel control circuit connected to direct said memory device and said photosensitive semiconductor device to a plurality of controlled modes, said plurality of controlled modes including an erase mode in which at least a portion of an electric charge is removed from said one of said floating gate, said Ferro-magnetic gate or said Ferro-electric gate to place said memory device in an initial state for exposure to said one of said floating gate, said Ferro-magnetic gate or said Ferro-electric gate electromagnetic radiation, an exposure mode in which said one of said floating gate, said Ferro-magnetic gate or said Ferro-electric gate is charged at least partially in response to a voltage at a terminal of said photosensitive semiconductor device, said voltage at said terminal corresponding to exposure of said photosensitive semiconductor device to said electromagnetic radiation from said image, and a read mode in which a predetermined voltage is provided at said control gate of said one of said floating gate, said Ferro-magnetic gate or said Ferro-electric gate of said memory device and a current flow between said drain and said source of said memory device is indicative of the charge placed on said one of said floating gate, said Ferro-magnetic gate or said Ferro-electric gate during said exposure mode;
• an image sensor readout circuit connected to obtain image data from each of said pixels during said read mode;
• a frame grabber connected to arrange image data obtained by said image sensor readout into an image frame.

A method as claimed in claim 27 wherein said step of driving said pixel in said exposure mode comprises:

• driving said FET switch and said diode each into a non-conductive state;
• driving said cathode of said photodiode to an exposure voltage level;
• and
• driving the voltage across said drain and source of said floating gate semiconductor device to a voltage sufficient to charge said floating gate in response to voltage levels at said anode of said photodiode.