Display panel and device utilizing the same and pixel structure
AssigneeQuanta Display Inc.
InventorTsung-Lin Yeh
Life of this patent
Estimating the term…
Abstract
A display panel includes a first row line, a second row line, a first column line, a first transistor, and a second transistor. The second row line is parallel to the first row line. The first column line is vertical to the first row line and the second row line. The first transistor includes a first terminal, a second terminal, and a first control terminal coupled to the first row line. The second transistor includes a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line.
Claims26
A display panel, comprising:
- a first row line;
- a second row line parallel to the first row line;
- a first column line vertical to the first and second row lines;
- a first transistor comprising a first terminal, a second terminal, and a first control terminal coupled to the first row line;
- and
- a second transistor comprising a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line.
A display device, comprising:
- a row driving unit for providing a first row signal and a second row signal;
- a column driving unit for providing a first column signal;
- and
- a display panel comprising:
- a first row line for receiving the first row signal;
- a second row line, parallel to the first row line, for receiving the second row signal;
- a first column line, vertical to the first and second row lines, for receiving the first column signal;
- a first transistor comprising a first terminal, a second terminal, and a first control terminal coupled to the first row line;
- and
- a second transistor comprising a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line.
A pixel structure comprising:
- a first row line;
- a second row line parallel to the first row line;
- a third row line parallel to the first row line;
- a first column line vertical to the first and second row lines;
- a first transistor comprising a first terminal, a second terminal, and a first control terminal coupled to the first row line;
- a second transistor comprising a third terminal coupled to the first column line, a fourth terminal coupled to the first terminal, and a second control terminal coupled to the second row line;
- a third transistor comprising a fifth terminal, a sixth terminal, and a third control terminal coupled to the second row line;
- and
- a fourth transistor comprising a seventh terminal coupled to the first column line, a eighth terminal coupled to the fifth terminal, and a fourth control terminal coupled to the third row line;
- wherein during a first period, the first and second row lines are simultaneously enabled and a first data signal is transmitted to the first and second transistors through the first column line, during a second period, the second row line is enabled and a second data is transmitted to the second transistor through the first column line, during a third period, the second and third row lines are simultaneously enabled and a third data signal is transmitted to the second, third, and fourth transistors through the first column line, during a fourth period, the third row line is enabled and a fourth data is transmitted to the fourth transistor through the first column line, and during a fifth period, the second row line is enabled and a fifth data is transmitted to the second transistor through the first column line.
Dependencies are inferred from the claim text.