Pulse width modulation in digital power amplifier
AssigneeSamsung Electronics Co., Ltd.
InventorJae-Wook Lee
Life of this patent
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Abstract
For PWM (pulse width modulation), a counter generates a count signal by counting a clock signal 2n times for one period of the count signal. A PWM circuit generates a PWM signal from an n-bit pulse code modulation (PCM) data. The PWM signal includes a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data. A same pulse width for the first and second pulses is determined by a respective value of each bit of the n-bit PCM data excluding the most and least significant bits of the n-bit PCM data.
Claims21
A pulse width modulation (PWM) method, comprising:
- generating a count signal by counting a clock signal 2n times for one period of the count signal;
- receiving an n-bit pulse code modulation (PCM) data;
- and
- generating a PWM (pulse width modulation) signal including a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data, wherein a same pulse width for the first and second pulses is determined by a respective value of each bit of the n-bit PCM data excluding a most significant bit and a least significant bit of the n-bit PCM data.
An apparatus for PWM (pulse width modulation), comprising:
- a counter for generating a count signal by counting a clock signal 2n times for one period of the count signal;
- and
- a PWM (pulse width modulation) circuit for generating a PWM (pulse width modulation) signal from an n-bit pulse code modulation (PCM) data, the PWM signal including a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data, wherein a same pulse width for the first and second pulses is determined by a respective value of each bit of the n-bit PCM data excluding a most significant bit and a least significant bit of the n-bit PCM data.
A digital power amplifier comprising:
- a counter for generating a count signal by counting a clock signal 2n times for one period of the count signal;
- a PWM (pulse width modulation) circuit for generating a PWM (pulse width modulation) signal from an n-bit pulse code modulation (PCM) data, the PWM signal including a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data, wherein a same pulse width for the first and second pulses is determined by a respective value of each bit of the n-bit PCM data excluding a most significant bit and a least significant bit of the n-bit PCM data;
- and
- a PWM (pulse width modulation) amplifying circuit for generating a current that drives a load according to the PWM signal.
Dependencies are inferred from the claim text.