Receiver with colpitts differential oscillator, colpitts quadrature oscillator, and common-gate low noise amplifier

An apparatus, comprising:

• a Colpitts differential oscillator having:
• a first Colpitts single-ended oscillator, the first single-ended Colpitts oscillator having a first transistor, the first transistor having a gate and a drain;
• and
• a second Colpitts single-ended oscillator, the second Colpitts single-ended oscillator having a second transistor, the second transistor having a gate and a drain,
• wherein the gate of the first transistor is coupled to the drain of the second transistor, and
• wherein the gate of the second transistor is coupled to the drain of the first transistor M304.

An apparatus, comprising:

• a Colpitts quadrature oscillator having:
• a first Colpitts differential oscillator having a first output;
• and
• a second Colpitts differential oscillator having a second output,
• wherein the first output is coupled to the second Colpitts differential oscillator, and
• wherein the second output is coupled to the first Colpitts differential oscillator.

An apparatus, comprising:

• a first transistor having a source, a drain, and a gate;
• a second transistor having a source, a drain, and a gate;
• and
• a transformer having a primary and a secondary,
• wherein the source of the first transistor is coupled to a first terminal of the primary and to an input terminal of the apparatus,
• wherein the second terminal of the primary is coupled to VSS, wherein the gate of the first transistor is coupled to a first terminal of the secondary,
• wherein the second terminal of the secondary is coupled to a bias voltage,
• wherein the drain of the first transistor is coupled to the source of the second transistor,
• wherein the gate of the second transistor is coupled to VDD,
• wherein the drain of the second transistor is coupled to a first terminal of an inductor and to a first terminal of a first capacitor,
• wherein the second terminal of the inductor is coupled to VDD, wherein the second terminal of the first capacitor is coupled to a first terminal of the second capacitor, and
• wherein the second terminal of the second capacitor is coupled to an output terminal of the apparatus.

A method of operating an amplifier, comprising

• applying an input voltage to the source of a transistor;
• generating a small signal current flow to a load impedance;
• and
• introducing a negative amplification between a source of the transistor and a gate of the transistor.

An apparatus, comprising:

• a differential common-gate amplifier having:
• a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, each having a first terminal and a second terminal;
• a first transistor, a second transistor, a third transistor, and a fourth transistor, each having a source, a drain, and a gate;
• a transformer having a primary and a secondary, the primary and the secondary each having a first terminal and a second terminal;
• a first inductor and a second inductor, each having a first terminal and a second terminal;
• a positive input node;
• a positive output node;
• a negative input node;
• and
• a negative output node,
• wherein the positive input node is coupled to the first terminal of the first capacitor,
• wherein the second terminal of the first capacitor is coupled to the first terminal of the transformer primary and to the source of the first transistor,
• wherein the gate of the first transistor is coupled to the first terminal of the transformer secondary,
• wherein the second terminal of the transformer secondary is coupled to the gate of the third transistor,
• wherein the second terminal of the transformer primary is coupled to the source of the third transistor and to the first terminal of the third capacitor,
• wherein the second terminal of the third capacitor is coupled to the negative input node;
• wherein the drains of the first and third transistors are coupled to the sources of the second and fourth transistors, respectively;
• wherein the drains of the second and fourth transistors are coupled to the first terminals of the second and fourth capacitors, respectively;
• wherein the second terminals of the second and fourth capacitors, are coupled to the positive output node and the negative output node, respectively, and to the first terminals of the first and second inductors, respectively, and
• wherein the second terminals of the first and second inductors are coupled to Vdd.