Level translator for adapting a signal to a voltage level
AssigneeBroadcom Corporation
InventorsErol Arslan, Ovidiu Bajdechi
Life of this patent
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Abstract
A level translator for translating a digital signal from a first voltage level to another voltage level having a higher voltage assigned to the high state of the signal comprises a latch and a pair of N-MOS transistors being coupled to the latch. This design is improved in that the N-MOS transistors are native thick oxide N-MOS transistors, each having a thin oxide layer N-MOS transistor coupled to native thick oxide transistors for reducing leakage current and improving speed in the transient state.
Claims13
A circuit for translating a digital input signal from a first voltage level to a digital output signal of a second, higher voltage level, having a first input connector for receiving the digital input signal and a second input connector for receiving the inverted digital input signal, a first output connector for delivering the digital output signal and a second output connector for delivering the inverted digital output signal, a first voltage supply connector coupled to the high potential of a voltage supply source and a second voltage supply connector coupled to the reference voltage of the voltage supply source,
- comprising:
- a latch coupled to the first voltage supply connector, the higher voltage level being the output voltage level of a first and second output connector of the latch;
- a first and a second N-MOS transistor, the first N-MOS transistor coupled to the first output connector of the latch and the second N-MOS transistor coupled to the second output connector of the latch respectively, and wherein the state of the first transistor is controlled by the state of the first input connector and the state of the second N-MOS transistor is controlled by the state of the second input connector respectively;
- a first and a second switching device, the first switching device connecting the drain of the first N-MOS transistor to the second voltage supply connector and the second switching device connecting the drain of the second N-MOS transistor to the second voltage supply connector, wherein the state of the first switching device is controlled by the state of the first input connector and the state of the second switching device is controlled by the state of the second input connector and wherein the switching time of first and second switching device into the insulating OFF-state is shorter than that of the first and second N-MOS transistor.
Dependencies are inferred from the claim text.