Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit
AssigneeMicron Technology, Inc.
InventorTyler Gomm
Life of this patent
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Abstract
A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.
Claims40
A duty cycle correction circuit for generating a correction signal for changing a phase relationship of first and second complementary clock signals to provide duty cycle corrected clock signals, the duty cycle correction circuit comprising:
- a first circuit operable to generate a first signal indicative of a time period of a high-cycle of the first clock signal;
- a second circuit operable to generate a second signal indicative of a time period of a low-cycle of the first clock signal;
- and
- an error calculation circuit coupled to the first and second circuits and operable to monitor the first and second signals and further operable to generate the correction signal in response to the first and second signals.
A duty cycle correction circuit, comprising:
- a measuring circuit operable to generate signals indicative of a time difference between a high-portion and a low portion of a clock signal;
- and
- a duty cycle error calculation circuit coupled to the measuring circuit and operable to generate a control signal responsive to changes in the time difference between the high- and low-portions of the clock signal as represented by the signals generated by the measuring circuit, the control signal indicative of a phase correction between the clock signal and a complementary clock signal due to the changes in the time difference between the high- and low-portions of the clock signal.
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write buffer circuits coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- a clock generator coupled to the read/write buffer circuits, the clock generator operable to generate output clock signals synchronized with corresponding input clock signals;
- and
- a duty cycle correction circuit, comprising:
- a measuring circuit operable to generate signals indicative of a time difference between a high-portion and a low portion of one of the input clock signals;
- and
- a duty cycle error calculation circuit coupled to the measuring circuit and operable to generate a control signal responsive to changes in the time difference between the high- and low-portions of the input clock signal as represented by the signals generated by the measuring circuit, the control signal indicative of a phase correction between the input clock signal and a complementary input clock signal due to the changes in the time difference between the high- and low-portions of the input clock signal.
A processor-based system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write buffer circuits coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- a clock generator coupled to the read/write buffer circuits, the clock generator operable to generate output clock signals synchronized with corresponding input clock signals;
- and
- a duty cycle correction circuit, comprising:
- a measuring circuit operable to generate signals indicative of a time difference between a high-portion and a low portion of one of the input clock signals;
- and
- a duty cycle error calculation circuit coupled to the measuring circuit and operable to generate a control signal responsive to changes in the time difference between the high- and low-portions of the input clock signal as represented by the signals generated by the measuring circuit, the control signal indicative of a phase correction between the input clock signal and a complementary input clock signal due to the changes in the time difference between the high- and low-portions of the input clock signal.
A method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal, the method comprising:
- detecting changes to a time difference between high- and low-portions of the first clock signal;
- and
- generating the correction signal in response to and accordance with the detected changes.
A method for generating a delay control signal to adjust a delay circuit for maintaining a phase relationship between a first clock signal and a second complementary clock signal, the method comprising:
- generating the delay control signal responsive to changes to a time difference between first and second portions of the first clock signal, the delay control signal indicative of a delay adjustment due to the changes in the time difference to maintain the phase relationship between the first clock signal and the second complementary clock signal.
Dependencies are inferred from the claim text.