Timing adjustment circuit
AssigneeElpida Memory, Inc.
InventorToru Ishikawa
Life of this patent
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Abstract
Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output data of the three flip-flops coincide with one another. If all the output data coincide with one another, the latch timing is maintained, whereas if the output data of the flip-flop latching the data signal at a fastest or latest timing differs from the output data of the flip-flop latching the data signal at the central timing, the judging circuit changes the variable timing to obtain a suitable latch timing.
Claims11
A timing adjustment circuit for controlling timing for latching a data signal based on an external timing signal, said timing adjustment circuit comprising:
- a variable delay circuit for delaying said external timing signal by a variable delay time to generate a delayed timing signal;
- a first latch circuit for latching said data signal based on a first clock signal having a specific phase relationship with respect to said delayed timing signal;
- a second latch circuit for latching said data signal based on a second clock signal having a first delay time with respect to said first clock signal;
- a third latch circuit for latching said data signal based on a third clock signal having a second delay time with respect to said first clock signal, said second delay time being larger than said first delay time;
- and
- a judging circuit for comparing output data of said first through third latch circuits among each other, to control said variable delay time based on a result of comparison.
Dependencies are inferred from the claim text.