Delay-locked loop circuits

A method of operating a delay-locked loop (DLL) circuit, the method comprising:

• (a) providing a variable delay line comprising a plurality of nominally identical delay stages connected in series, the delay at each stage being adjustable, the delay line including an input node of the first of said identical stages, one or more intermediate nodes at which the output of one of said identical stages is coupled to the input of a next stage, and an end node comprising the output of a last one of said identical stages in the delay line;
• (b) receiving a periodic reference signal and feeding said periodic reference signal via a delay line input path for to the input node of the delay line;
• (c) deriving from respective ones of said nodes a plurality of output signals having a desired phase relationship with one another;
• and
• (d) controlling the delays of the stages within the variable delay line automatically such that the total delay over a number of said stages corresponds in a known manner to a period of the periodic reference signal,
• wherein said controlling step (d) is performed by comparing the phase of first and second differently delayed versions of the reference signal which are both derived via respective output paths from respective nodes within the variable delay line, said nodes being separated only by a plurality of identical delay stages.

A delay-locked loop (DLL) circuit having a reference signal input for a receiving a periodic reference signal, the DLL circuit comprising:

• (a) a variable delay line comprising a plurality of delay stages connected in series, a first stage being arranged to receive the reference signal from said reference signal input, the delay at each stage being adjustable in response to a delay control signal;
• (b) a phase comparator arranged to receive first and second versions of said reference signal, at least the second version being delayed via said delay line, the phase comparator responding to the relative order of transitions in said first and second versions to indicate the polarity of a phase error between them;
• and
• (c) a delay control signal generator responsive to said phase error indication for modifying the delay control signal applied to the variable delay line so as to counter the indicated phase error,
• wherein the DLL circuit further comprises start-up control circuitry arranged (i) to receive a pre-start signal and to modify the delay control signal so as to minimise the delay of the variable delay line prior to starting operation and (ii) to cause said phase comparator to ignore a first transition in the first version of the reference signal in determining the relative order of transitions in the first and second versions of the reference signal.

A method of starting a delay-locked loop (DLL) circuit in response to a periodic reference signal, the DLL circuit comprising:

• (a) a variable delay line comprising a plurality of delay stages connected in series, a first stage being arranged to receive the reference signal from said reference signal input, the delay at each stage being adjustable in response to a delay control signal,
• (b) a phase comparator arranged to receive first and second versions of said reference signal, at least the second version being delayed via said delay line, the phase comparator responding to the relative order of transitions in said first and second versions to indicate the polarity of a phase error between them;
• and
• (c) a delay control signal generator responsive to said phase error indication for modifying the delay control signal applied to the variable delay line so as to counter the indicated phase error, the phase comparator and delay control signal generator together forming a feedback control circuit,
• the start-up method comprising the steps of (i) prior to operation of said feedback control circuit, modifying the delay control signal so as to minimise the delay of the variable delay line and (ii) upon commencing operation of said feedback control circuit, causing said phase comparator to ignore a first transition in the first version of the reference signal in determining the relative order of transitions in the first and second versions of the reference signal.