Methods and systems for locally generating non-integral divided clocks with centralized state machines
AssigneeInternational Business Machines Corporation
InventorsWilliam Huott, Charlie Hwang, Timothy McNamara
Life of this patent
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Abstract
A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
Claims29
A method for locally generating a ratio clock on a chip, comprising:
- generating a global clock signal having a global clock cycle;
- providing a centralized state machine, the state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter;
- providing the control signal to staging latches, the staging latches generating a clock high signal and a clock low signal,
- providing local pass gate for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
A method for locally generating a ratio clock, comprising:
- generating a global clock signal having a global clock cycle;
- providing a centralized clock control unit including a first state machine and a second state machine, the first state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the first state machine generating a generating a clock high signal having a pattern corresponding to a target divided ratio clock when the global clock is high;
- the second state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the second state machine generating a generating a clock low signal having a pattern corresponding to the target divided ratio clock when the global clock is low;
- providing local pass gate for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
Circuitry for locally generating a ratio clock on a chip, comprising:
- circuitry for generating a global clock signal having a global clock cycle;
- a centralized state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter;
- staging latches receiving the control signal and generating a clock high signal and a clock low signal;
- a local pass gate receiving the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
Dependencies are inferred from the claim text.