US 2007/0176652 A1 · Method for locally generating non-integral divided clocks with centralized state machines

Abstract

A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

Claims9

Dependent claims

A method for locally generating a ratio clock on a chip, comprising:

generating a global clock signal having a global clock cycle;
providing a centralized state machine, the centralized state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state macnine generating a control signal in response to the counter;
providing the control signal to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle;
providing local pass gate for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

1 more element

Dependencies are inferred from the claim text.

Method for locally generating non-integral divided clocks with centralized state machines

Life of this patent

Method for locally generating non-integral divided clocks with centralized state machines

Life of this patent

Abstract

Claims9