Programmable logic function generator using non-volatile programmable memory switches

A 2-input programmable logic generator (PLG) to perform as a 2-input look-up table with minimum number of PMOS transistors, the PLG comprising:

• pass gates for routing signals to an output of the PLG, wherein the pass gates are controlled by a first input to the PLG;
• programmable switches for routing a second input signal and a high-logic voltage to the pass gates, wherein the switches are NMOS transistors, gates of which are controlled by programmable memory units;
• inverters for inverting signals;
• and
• a configuration wherein:
• the second input, the high-logic voltage, or their inverses are programmably routed to each of the pass gates.

A 2-input programmable logic generator (PLG), comprising:

• inverting means for inverting signals;
• transmitting means for controllably routing signals to an output of the PLG, wherein a first input signal to the PLG controls the transmitting means;
• and
• switching means for routing a second input signal, a voltage Vdd, or their inverses to the transmitting means.

A 2-input programmable logic generator (PLG), comprising:

• two pass gates for routing signals to an output of the PLG;
• eight programmable switches for routing signals to the pass gates;
• three inverters for inverting signals;
• and
• a configuration wherein:
• a first input to the PLG and a voltage Vdd are connected to a first node through a first and a second switch, respectively, and wherein the first node is connected to a first pass gate through a third switch and also connected through a series combination of a first inverter and a fourth switch;
• the first input to the PLG and the Vdd are connected to a second node through a fifth and a sixth switch, respectively, and wherein the second node is connected to a second pass gate through a seventh switch and also connected through a series combination of a second inverter and an eight switch;
• the pass gates are controlled by a combination of a second input signal to the PLG, its inverse, or both, wherein the inverse is produced by a third inverter;
• and
• programming of the first through the eighth switches routes the first input, the Vdd, or their inverses to the first pass gate, the second pass gate, or both, from which they are controllably routed to the PLG output.

A method of generating logic functions of two input signals by programming switches, the method comprising:

• connecting a first input and a voltage Vdd to a first node through a first and a second programmable switch, respectively;
• connecting the first node to a first pass gate through a third switch and also through a series combination of a first inverter and a fourth switch;
• connecting the first input and the Vdd to a second node through a fifth and a sixth programmable switch, respectively;
• connecting the second node to a second pass gate through a seventh switch and also through a series combination of a second inverter and an eight switch;
• and
• controlling the first and the second pass gates by a combination of a second input signal.