Domino logic circuit techniques for suppressing subthreshold and gate oxide leakage
AssigneeWisconsin Alumni Research Foundation
InventorsVolkan Kursun, Zhiyu Liu
Life of this patent
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Abstract
Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology may be utilized to place idle domino logic circuits into a low leakage state. The circuits may significantly lower the total leakage power as compared to the standard dual threshold voltage domino logic circuits at both the high and low die temperatures. The energy overheads of the circuit techniques may be low, justifying the activation of the proposed sleep schemes by providing net savings in total power consumption during short idle periods.
Claims23
A domino logic circuit comprising:
- a precharge circuit for precharging a dynamic node to a predetermined value;
- an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;
- an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node;
- and
- a sleep circuit consisting of a single sleep transistor for inhibiting current to the output circuit during a sleep mode.
A domino logic circuit comprising:
- a precharge circuit for precharging a dynamic node to a predetermined value;
- an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;
- an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node;
- and
- a sleep circuit consisting of one or more PMOS transistors for reducing current to the output circuit or discharging the dynamic node during a sleep mode.
The domino logic circuit of claim 13, wherein at least one of the three PMOS transistors has a higher threshold voltage than at least one remaining transistor of the three PMOS transistors.
A domino logic circuit comprising:
- a precharge circuit for precharging a dynamic node to a predetermined value;
- an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;
- an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node;
- a keeper circuit for keeping the dynamic node at the predetermined value after the precharge circuit precharges the dynamic node to the predetermined value, the keeper circuit including an input that is connected to the output of the output circuit;
- and
- a sleep circuit for reducing current to at least one of the output circuit or the keeper circuit during a sleep mode.
Dependencies are inferred from the claim text.