US 2007/0176641 A1 · Low swing domino logic circuits

Abstract

Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper and lower boundaries of the voltage swing at the dynamic node may be different from the upper and lower boundaries of the voltage swing at the output node. For example, the voltage swing at the dynamic node may be less than the voltage swing at the output node, optimized for speed or power consumption. As another example, the voltage swing at the dynamic node may be greater than the voltage swing at the output node, optimized for speed or power consumption. Further, the domino logic circuit may use dual Vt thereby reducing the short-circuit current during operation. Meanwhile, full voltage swing signals may be maintained at the inputs and outputs for high speed operation. The low swing circuit techniques are provided that modify the output voltage swing of a domino gate, thereby reducing the active mode power consumption.

Claims21

Dependent claims

A domino logic circuit comprising:

a precharge circuit for precharging a dynamic node to a predetermined value;
an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;
an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node;
and
wherein a voltage swing at the dynamic node is different from a voltage swing at the output for the output circuit, and
wherein at least one transistor in the precharge circuit or the output circuit has a higher threshold voltage than at least some of the transistors in the input circuit in order to reduce short-circuit current.

3 more elements

Dependencies are inferred from the claim text.

Low swing domino logic circuits

Life of this patent

Low swing domino logic circuits

Life of this patent

Abstract

Claims21