Low leakage and data retention circuitry
AssigneeMOSAID Delaware, Inc.
InventorsBarry Hoberman, Daniel Hillman, William Walker, John Callahan, Michael Zampaglione, Andrew Cole
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Abstract
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
Claims33
A data retention circuit apparatus, the apparatus comprising:
- an input/output pad cell comprising level shifter circuitry with inputs and outputs;
- output latching circuitry comprising at least two transistors coupled to the outputs of the level shifter circuitry and configured to retain a state of the level shifter circuitry based on the state of the inputs;
- and
- a leakage optimization circuit configured to decrease leakage power in tandem with the state retention of the output latching circuitry.
A system for controlling power consumption within an integrated circuit, the system comprising:
- a power island including a first circuit, the first circuit configured to:
- receive input signals;
- receive a hold signal;
- process the input signals;
- retain data in a sleep state having low leakage;
- and
- retain the data based on the hold signal;
- a sleep transistor coupled to the first circuit, the sleep transistor configured to:
- receive a negative voltage sleep signal;
- and
- reduce power consumption of the first circuit in the sleep state, wherein the first circuit has low leakage based on the sleep signal while simultaneously retaining the data.
Dependencies are inferred from the claim text.