Output circuit
AssigneeFujitsu Limited
InventorYukihito Kawabe
Life of this patent
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Abstract
An output circuit including: a tri-state output circuit capable of outputting high-impedance state, high-level state, and low-level state, in which the high-level state and low-level state are low-impedance state, and switching the high-impedance state and the low-impedance state in accordance with a first control signal; and a delay circuit outputting the first control signal to the tri-state output circuit by inputting a second control signal and delaying the second control signal so that timing delay time of the second control signal switching the high-impedance state to the low-impedance state is longer than the timing delay time of the second control signal switching the low-impedance state to the high-impedance state, is provided.
Claims17
An output circuit comprising:
- a tri-state output circuit capable of outputting high-impedance state, high-level state, and low-level state, in which the high-level state and low-level state are low-impedance state, and switching the high-impedance state and the low-impedance state in accordance with a first control signal;
- and
- a delay circuit outputting the first control signal to said tri-state output circuit by inputting a second signal and delaying the second control signal so that timing delay time of the second control signal switching the high-impedance state to the low-impedance state is longer than the timing delay time of the second control signal switching from the low-impedance state to the high-impedance state.
Dependencies are inferred from the claim text.