FPGA architecture at conventional and submicron scales

A reconfigurable logic device, comprising:

• a look-up table (LUT), comprising:
• a plurality of LUT input signals;
• an address decoder operably coupled to the plurality of LUT input signals, the address decoder configured to generate a plurality of product terms;
• an array of programmable impedance devices operably coupled to the plurality of product terms, each programmable impedance device comprising:
• a first electrode operably coupled to one of the plurality of product terms;
• a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode;
• and
• a programmable material disposed between the first electrode and the second electrode at least at the junction, the programmable material operably coupling the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance;
• at least one LUT output signal operably coupled to at least one of the array of programmable impedance devices;
• and
• at least one storage element configured for sampling the at least one LUT output signal.

A method of tuning a programmable impedance, comprising:

• supplying a reconfigurable logic device including a one-dimensional array of programmable impedance devices configured as a plurality of substantially parallel first nodes in a first direction and a second node in a second direction, wherein a programmable impedance device is present at a junction where each first node of the plurality of first nodes-crosses the second node;
• applying a current sink to the second node;
• and
• applying a positive voltage pulse to one first node of the plurality of first nodes, the positive voltage pulse having a peak voltage sufficient to decrease an impedance of the programmable impedance device at the junction between the one first node and the second node.