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US 2007/0176621 A1Published application
Semiconductor wafer testing apparatus and method of testing semiconductor wafer
AssigneeRenesas Electronics Corporation
InventorTakahiro Tanamachi
Life of this patent
Estimating the term…
Abstract
In a method of testing a semiconductor wafer, semiconductor chips of a predetermined number are selected from among a plurality of semiconductor chips formed on a semiconductor wafer, and a first test is performed on I/O pins of each of the selected semiconductor chips. Then, a second test is performed on a part of the I/O pins of each of non-selected semiconductor chips as ones of the plurality of semiconductor chips other than the selected semiconductor chips.
Claims20
A method of testing a semiconductor wafer, comprising:
- selecting semiconductor chips of a predetermined number from among a plurality of semiconductor chips formed on a semiconductor wafer;
- performing a first test on I/O pins of each of said selected semiconductor chips;
- and
- performing a second test on a part of said I/O pins of each of non-selected semiconductor chips as ones of said plurality of semiconductor chips other than said selected semiconductor chips.
1 more element
A semiconductor wafer testing apparatus which tests semiconductor chips formed in regions of a semiconductor wafer, comprising:
- a CPU;
- a storage unit configured to store a semiconductor chip test program;
- and
- a communication unit configured to receive and hold a data signal sent from each of said semiconductor chips,
- wherein said CPU reads out and executes said semiconductor chip test program from said storage unit, and
- said CPU, based on said semiconductor chip test program:
- selects semiconductor chips of an optionally set number from a plurality of semiconductor chips formed in regions into which said semiconductor wafer is divided,
- performs a first test of test items on I/O
- acquires data signals for said test items through said communication unit to store in said storage unit,
- performs a second test of selected ones of the test items on at least one sampled from the I/O pins of each of non-selected semiconductor chips as ones of said plurality of semiconductor chips other than said selected semiconductor chips, and
- said test items contain necessary test items and said selected test items.
8 more elements
A semiconductor wafer testing apparatus which tests semiconductor chips formed in regions of a semiconductor wafer, comprising:
- a CPU;
- a storage unit configured to store a semiconductor chip test program;
- and
- a communication unit configured to receive and hold a data signal sent from each of said semiconductor chips,
- wherein said CPU reads out and executes said semiconductor chip test program from said storage unit, and
- said CPU, based on said semiconductor chip test program:
- selects semiconductor chips of an optionally formed in regions into which said semiconductor wafer is divided,
- performs a first test of test items on each of said selected semiconductor chips,
- performs a second test of necessary ones of the test items on each of non-selected semiconductor chips as ones of said plurality of semiconductor chips other than said selected semiconductor chips, said test items containing said necessary test items and selected test items,
- compares a cumulative defect percentage of each of said selected test items with a preset defect percentage,
- determines whether a third test of said selected test item should be performed on each of said non-selected semiconductor chips, based on the comparing result,
- when said cumulative defect percentage of said selected test item is higher than said preset defect percentage, performs said third test of said test item on each of said non-selected semiconductor chips,
- when said cumulative defect percentage of said selected test item is not higher than said preset defect percentage, calculates a pin defect percentage for each of I/O pins of each of said non-selected
- selects test omissible I/O pins of each of said non-selected semiconductor chips based on said in defect percentage,
- performs said third test of said selected test items on a remaining I/O pin as at least one of said I/O pins other than said test omissible I/O pins in each of said non-selected semiconductor chips, and
- updates said cumulative defect percentage for each of said selected test items and for the remaining I/O pin.
13 more elements
A semiconductor wafer testing apparatus comprising:
- a CPU;
- a storage unit configured to store a semiconductor chip test program;
- and
- a communication unit configured to receive a semiconductor chips,
- wherein said CPU reads out and executes said semiconductor chip test program from said storage unit,
- said CPU, based on said semiconductor chip test program:
- selects semiconductor chips from a plurality of semiconductor chips formed on a semiconductor wafer,
- said communication unit receives the data signal from each of said I/O pins in each of said selected semiconductor chips and a part of said I/O pins in each of non-selected semiconductor chips as ones of said plurality of semiconductor chips other than said selected semiconductor chips, and
- said CPU performs, based on the data signals, a first test on said I/O pins in each of said selected semiconductor chips and the part of said I/O pins in each of said non-selected semiconductor chips.
6 more elements
A method of testing a semiconductor wafer, comprising:
- selecting semiconductor chips of a predetermined number from a plurality of semiconductor chips formed in a plurality of regions of a semiconductor wafer;
- performing a first test of test items on all of I/O pins of each of said selected semiconductor chips;
- and
- performing a second test of selected ones of the test items on at least one I/O pin in each of non-selected semiconductor chips as ones of said plurality of semiconductor chips other than said selected semiconductor chips based on a result of said first
1 more element
A method of testing a semiconductor wafer, comprising;
- selecting semiconductor chips of a predetermined number from a plurality of semiconductor chips formed in a plurality of regions of a semiconductor wafer;
- performing a first test of test items on each of said selected semiconductor chips;
- performing a second test of necessary ones among the test items on each of non-selected semiconductor chips as ones of said plurality of semiconductor chips other than said selected semiconductor chips, wherein said test items are grouped into said necessary test items and selected test items;
- comparing a cumulative defect percentage for each of selected test items as ones of the test items other than said necessary test items and a preset defect percentage to determine whether a third test of said selected test items should be performed on each of said non-selected semiconductor chips;
- performing said third test of each of said selected test items on each of said non-selected semiconductor chips when said cumulative defect percentage for said selected test item is higher than said preset defect percentage;
- I/O pins of each of said non-selected semiconductor chips when said cumulative defect percentage for said selected test item is not higher than said preset defect percentage;
- determining test omissible ones of said I/O pins of each of said non-selected semiconductor chips based on the calculated detect percentages;
- and
- performing said third test of said selected test item on ones of said I/O pins other than the test omissible I/O pins in each of said non-selected semiconductor chips.
6 more elements
Dependencies are inferred from the claim text.