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AssigneesHitachi ULSI Systems Co., Ltd., Renesas Technology Corp.
InventorsHiroshi Toyoshima, Masahiko Nishiyama
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The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin. And, since the phase compensating resistor can take a considerably high resistance, the same characteristic can be achieved with a low capacitance of the phase compensating capacitor; thereby, the phase compensation becomes possible with a resistor and a capacitor having a smaller size than the pole/zero compensation with the internal supply voltage.
A semiconductor memory device which has a power supply circuit, the power supply circuit comprising:
A semiconductor memory device which has a power supply circuit, the power supply circuit comprising:
Dependencies are inferred from the claim text.