Power Semiconductor Component Having Chip Stack
AssigneeInfineon Technologies AG
InventorRalf Otremba
Life of this patent
Estimating the term…
Abstract
A power semiconductor component (2) has a chip stack, which contains a first chip (10), a second chip (6) and a third chip (8), where at least the second chip (6) and the third chip (8) are the same height. The power semiconductor component (2) also has a package in which the first chip (10), the second chip (6) and the third chip (8) are placed. The second chip (6) and the third chip (8) are mounted side by side on a lead (4), and the first chip (10) rests both on the second chip (6) and on the third chip (8).
Claims20
A power semiconductor component comprising a chip stack with a first chip, a second chip and a third chip,
- and having a package in which the first chip, the second chip and the third chip are placed,
- wherein the second chip and the third chip lie side by side on a lead, and the first chip is mounted both on the second chip and on the third chip.
A method for fabricating a power semiconductor component, comprising the following steps:
- mounting a second chip and a third chip side by side on a lead,
- mounting a first chip such that the first chip rests on the second chip and on the third chip,
- bonding the contact surfaces on the upper faces of the first chip, the second chip and the third chip by means of bonding wires,
- encapsulating the first chip, the second chip and the third chip with a molding compound.
A power semiconductor component comprising a chip stack with a first chip, a second chip and a third chip,
- and having a package in which the first chip, the second chip and the third chip are placed, wherein
- the second chip and the third chip lie side by side on a lead, and the first chip is mounted both on the second chip and on the third chip, and wherein
- the first chip is mounted symmetrically on the second chip and on the third chip such that the support surface of the first chip on the second chip is equal in area to the support surface of the first chip on the third chip.
Dependencies are inferred from the claim text.