Split gate memory cell in a FinFET

A memory device, comprising:

• a first semiconductor fin having a first sidewall and a second sidewall, a drain region, a source region, a first channel between the source region and the drain region and along the first sidewall, a second channel between the source region and drain region and along the second sidewall, carriers travel substantially horizontally in the first channel region and the second channel region;
• a gate dielectric along a first portion of the first sidewall and along a first portion of the second sidewall;
• a select gate structure on the gate dielectric;
• a first storage layer along a second portion of the first sidewall and along a second portion of the second sidewall;
• a first control gate structure having a first portion adjacent to the first storage layer along the second portion of the first sidewall;
• and
• a second control gate structure having a first portion adjacent to the first storage layer along the second portion of the second sidewall.

A method of making a semiconductor device, the method comprising:

• forming a semiconductor fin on a wafer, the semiconductor fin having a first sidewall and a second sidewall opposite the first sidewall;
• forming a layer of select gate material over the wafer including over the semiconductor fin;
• forming a layer of charge storage material over the wafer including over the semiconductor fin;
• forming a layer of control gate material over the wafer including over the semiconductor fin;
• forming a select gate structure, wherein the forming the select gate structure includes patterning the layer of select gate material, wherein the select gate structure includes a first portion adjacent a first portion of the first sidewall;
• wherein the layer of charge storage material includes a portion adjacent a second portion of the first sidewall;
• forming a control gate structure, wherein the forming the control gate structure include patterning the layer of control gate material, the control gate structure includes a first portion adjacent to the portion of the layer of charge storage material adjacent a second portion of the first sidewall;
• wherein the semiconductor fin includes a first channel region, the first channel region includes a portion along the first sidewall, wherein carriers travel substantially horizontally in the first channel region, wherein a first portion of the first channel region along the first sidewall is located adjacent to the select gate structure, wherein a second portion of the first channel region along the first sidewall is located adjacent to the portion of the layer of charge storage material.