Hosting structure of nanometric elements and corresponding manufacturing method

A nanometric electronic device comprising at least a nanometric component hosted in a hosting structure, having:

• a substrate,
• a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and
• a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including a first discontinuous insulating layer and an upper layer, including in turn second conductive spacers
• each pair of said spacers of said second multi-spacer level defining, with a spacer of said first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of said first conductive spacers and of said second conductive spacers faced in said hosting seats.
• wherein said conductive spacers of said hosting structure defining respective conduction terminals of said at least one nanometric component.

A method for manufacturing a nanometric hosting structure comprising the following steps of:

• depositing, above a substrate, of a block seed having at least one side wall substantially perpendicular to said substrate;
• repeating n times, with n≧2, a step comprising a deposition, on said block seed and on said substrate, of alternating materials, and an anisotropic etching of said deposited layer, with realization, at each repetition, of at least a relative spacer substantially perpendicular to said substrate,
• said alternating materials being different for each pair of consecutive depositions, said n steps defining at least a first multilayer body comprising a plurality of first conductive and first insulating spacers of respectively a conductive material and an insulating material which can be chemically etched in a selective way,
• depositing, above said first multilayer body, of a first insulating layer,
• defining, above said first insulating layer of a second multilayer body realized, through the steps of:
• deposition of a second block seed on said first insulating layer, and
• repetition of m steps, with m≧3, each step comprising a deposition of a layer of alternating materials, and an anisotropic etching of said deposited layer, with realization, at each repetition, of a second spacer substantially perpendicular to said first insulating layer,
• said alternating materials being different for each pair of consecutive depositions, said second multilayer body comprising a plurality of second conductive and second insulating spacers realized with at least two materials, respectively a conductive material and an insulating material,
• said second spacers of said second multilayer body being realized transversally with respect to said first spacers of said first multilayer body,
• selective etching with respect to said insulating material of said second multilayer body and of said first insulating layer with removal of second insulating spacers and of exposed portions of said first insulating layer, realizing a plurality of spacers comprising portions of said first insulating layer and said second conductive spacers to form a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of said first conductive spacers and of said second conductive spacers faced in said hosting seats.

A hosting structure for hosting nanometric components, comprising:

• a substrate;
• a first layer having a plurality of alternating first conductive spacers and first insulating spacers;
• and
• a first array of spacer bars being arranged transversely on top of the first layer, each of said spacer bars comprising a first spacer pair overlying a first insulating layer, said spacer pair having a second conductive spacer adjoining a second insulating spacer wherein, the second conductive spacers alternate with the second insulating spacers across the first array of spacer bars.