Mixed-scale electronic interface
AssigneeHewlett-Packard Development Company, L.P.
InventorsGregory Snider, R. Williams
Life of this patent
Estimating the term…
Abstract
Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer.
Claims20
A nanoscale/microscale interface comprising:
- a predominantly microscale layer with a surface having regularly patterned pins;
- and
- a predominantly nanoscale layer comprising an ordered arrangement of pad-interconnected nanowire units, a first pad of a pad-interconnected nanowire unit overlying a first pin of the predominantly microscale layer to electrically interconnect the first pin to a second pin through a pad-interconnected nanowire unit overlying the second pin and connected to the first pad-interconnected nanowire unit through a conductive nanowire junction.
A method for fabricating a nanoscale/microscale interface, the method comprising:
- providing a substrate with a surface having regularly patterned conductive pins;
- fabricating, by nanoimprinting, a first nanoscale sub-layer above the substrate composed of a regular pattern of pad-interconnected nanowire units with pads of the pad-interconnected nanowire units overlying pins of the substrate;
- and
- fabricating, by nanoimprinting, a second nanoscale sub-layer above the first nanoscale sub-layer with pads of the pad-interconnected nanowire units overlying pins of the substrate.
Dependencies are inferred from the claim text.