High performance chip carrier substrate
AssigneeInternational Business Machines Corporation
InventorsJean Audet, Irving Memis
Life of this patent
Estimating the term…
Abstract
A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.
Claims30
A multilayer chip carrier, comprising:
- a layer of dielectric material having a plurality of signal pads formed thereon in a pattern of signal pads related to a pattern of signal pads within the footprint of at least one chip to be carried on said chip carrier, said plurality of signal pads including a first set of signal pads near the edge of said chip footprint each having a conductive line connected thereto extending beyond the edge of said chip footprint and a second set of signal pads each having a conductive line connected thereto extending to connect to respective signal pads positioned nearer the said edge of said chip footprint.
A multilayer chip carrier substrate, comprising:
- one layer of dielectric material having positioned thereon a plurality of signal pads some of which form a first set of signal pads having conductive lines connected thereto extending beyond the edge of the footprint of the chip to be attached thereto and some of which form a second set of signal pads having conductive lines connected thereto extending toward the edge of said footprint to connect to a third set of signal pads, said third set of signal pads having conductive vias connected thereto which are respectively connected to a corresponding set of said signal pads on another layer of dielectric material.
A multilayer chip carrier, comprising:
- a first layer of dielectric material having a plurality of signal pads formed thereon arranged in a pattern of signal pads related to signal pads within the footprint of at least one chip to be carried by said chip carrier, said plurality of signal pads including a first set signal pads near the edge of said chip footprint each having conductive lines connected thereto extending beyond the edge of said chip footprint and a second set of signal pads each having a conductive line connected thereto extending to connect to respective signal pads positioned closer to the edge of said chip footprint with said signal pads positioned closer to the edge of said chip footprint having conductive vias connected thereto extending through said first layer of dielectric material;
- a second layer of dielectric material having a set of signal pads arranged thereon respectively connected to said conductive vias extending through said first layer of dielectric material and having respective conductive lines connected thereto extending to respectively connect to further signal pads positioned closer to the edge of said chip footprint, said further signal pad having conductive vias connected thereto extending through said second layer of dielectric material;
- and
- a third layer of dielectric material having a set of signal pads arranged thereon respectively connected to the said conductive vias extending through said second layer of dielectric material and having conductive lines respectively connected thereto extending beyond the edge of said chip footprint.
A method of fanout redistribution of signal pads on a multilayer chip carrier, comprising:
- providing a layer of dielectric material having a plurality of signal pads formed thereon in a pattern of signal pads within the footprint of at least one chip to be carried therein;
- providing conductive lines connected to a first set of signal pads of said plurality of signal pads near the edge of said chip footprint extending beyond the edge of said chip footprint to allow signals from said first set of signal pads to escape said chip footprint;
- and
- moving a second set of signal pads of said plurality of signal pads closer to the edge the edge of said chip footprint.
Dependencies are inferred from the claim text.