Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
AssigneeSynopsys, Inc.
InventorsJianfeng Luo, Subarnarekha Sinha, Qing Su, Charles Chiang
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AssigneeSynopsys, Inc.
InventorsJianfeng Luo, Subarnarekha Sinha, Qing Su, Charles Chiang
Estimating the term…
One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.
A method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising:
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising:
An apparatus for predicting a manufacturing yield for a die within a semiconductor wafer, the apparatus comprising:
Dependencies are inferred from the claim text.