Processor having multiple instruction sources and execution modes
OwnerAnthony Jones, Paul Wasson +1inventors
InventorsAnthony Jones, Paul Wasson, Michael Butts
Life of this patent
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Abstract
A processor includes the standard mode of executing instructions from stored memory as well as a mode of executing from a separate instruction source. A programmable selector determines the source, and may be automatically programmed dependent on particular instructions. Streaming instructions from outside the processor provides an ability to have infinite program space. Further, booting processors in such an execution mode allows systems to be configured from external sources.
Claims34
A processor, comprising:
- a memory subsystem having random access to instructions stored in a memory;
- a streaming channel input, separate from the memory subsystem, for streaming instructions to the processor from a streaming channel;
- and
- a selector coupled to the memory subsystem and to the streaming channel input, the selector structured to choose an instruction from either the memory or the streaming channel.
A system of multiprocessors, comprising:
- a plurality of processors,
- a communication fabric interconnecting the plurality of processors, the communication fabric including a series of communication channels having data lines and protocol lines;
- at least one random access memory having instructions stored therein;
- wherein at least one of the plurality of processors includes:
- a memory input for accepting instructions from the random access memory;
- a channel input coupled to a selected one of the communication channels that is structured to stream instructions to the processor;
- and
- a selector coupled to the memory input and to the channel input and structured to choose an instruction from either the random access memory or the communication channel.
A method of operating a processor, comprising:
- executing an instruction from a first instruction source;
- receiving a signal to change execution modes;
- and
- executing an instruction from a second instruction source, wherein at least one of the sources is an instruction stream.
A method of operating a processor, comprising:
- operating in a channel execution mode using instructions from a channel;
- storing instructions that were received from the channel into a memory;
- and
- switching to a memory execution mode to operate on the instructions from the memory.
Dependencies are inferred from the claim text.