Microprocessor for executing byte compiled java code

A microprocessor for executing bytecode compiled from an objected oriented programming language in hardware comprising:

• a RISC processor, the RISC processor configured to be an embedded processor;
• a first module to execute a set of instructions in bytecode in the RISC processor;
• a RISC module to execute a set of instructions as microcode in the RISC processor, the set of instructions to be executed as microcode being more complex than the set of instructions in bytecode, said RISC module including means for handling interrupts and a flexible hardware interface to control highly specialized highly peripheral devices;
• and
• a databath shared by both modules, said datapath including a register file shared by both modules, said register file including:
• i) a plurality of elements shared by the first module and the RISC module, the first module seeing a portion of these elements as a circular operand stack and a remaining portion as storage registers, the RISC module seeing the plurality of elements as a register file;
• ii) a control bit tracking which module is in operation;
• iii) a program counter containing the address of an instruction to be executed;
• iv) a program counter base register storing the address of a new method to be invoked;
• v) a local variable address to store base address information for local variables in a method;
• vi) a constant pool address to store the base address for the constant pool in a class;
• vii) a stack pointer to track where the top of the operand is;
• and
• viii) a RISC stack pointer to point where the RISC can temporarily store variables if the register file is full.

A method of executing bytecode compiled from an object oriented programming language in an embedded RISC processor, said method comprising:

• executing a set of instruction as bytecode in the processor with a first module;
• executing a set of instructions as microcode with the RISC module, the set of instructions to be executed as microcode being more complex than the set of bytecode instructions;
• interrupting the processor when an instruction too complex for execution by the first module appears;
• confirming that a set of implementation specific conditions require the processor to be interrupted;
• executing the complex instruction separately from other instructions in the RISC module;
• storing a return address on top of a stack in the RISC module;
• and
• returning to the first module when the RISC module has finished executing the complex instruction.

A microprocessor for executing bytecode compiled from an object oriented programming language in hardware comprising:

• a RISC processor, the RISC processor configured to be an embedded processor;
• a first module to execute a set of instructions in bytecode in the RISC processor;
• a RISC module to execute a set of instructions as microcode in the RISC processor, said RISC module including means for handling interrupts and a flexible hardware interface to control highly specialized devices;
• and
• a datapath in the RISC processor shared by both modules, said datapath including a register file shared by both modules, said register file having a local variable base address to store base address information for local variables in a method, and said register file having a plurality of elements shared by the first module and the RISC module, the first module seeing a first portion of the plurality of elements as a circular operand stack and a remaining portion of the plurality of elements as storage registers, the RISC module seeing the plurality of elements as a register file.