Design method and architecture for power gate switch placement and interconnection using tapless libraries
AssigneeSequence Design, Inc.
InventorGerald Frenkil
Life of this patent
Estimating the term…
Abstract
A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these standard cells may be provided by the switch cells or by specialized tap cells. The tapless standard cells may include only a context-sensitive rail, which may be configured to be a virtual ground rail by a power gating connection to a switch cell or by a direct connection to a power supply or ground rail.
Claims25
A switch cell comprising:
- a first conductive trace positioned at a predetermined distance relative to a border of the switch cell and laid out along a predetermined direction;
- a second conductive trace positioned at the predetermined distance relative to the border of the switch cell and laid out along the predetermined direction, the first and second conductive traces being spatically separated from each other;
- and
- a transistor providing a selectably enabled conduction path between the first conductive trace and the second conductive trace.
An integrated circuit comprising a plurality of rows of cells, each comprising:
- a plurality of logic cells each having a conductive trace positioned at the predetermined distance relative to a common border of the logic cell and laid out along a predetermined direction, the logic cells being laid out abutting each other such that the conductive traces form a power rail along a length of the logic cells;
- and
- a switch cell comprising:
- a first conductive trace abutting the power rail;
- a second conductive trace spatically separated from each other, and wherein the second conductive trace being laid out also at the predetermined distance the common border;
- and
- a transistor providing a selectably enabled conduction path between the first conductive trace and the second conductive trace.
A method for laying out an integrated circuit, comprising:
- providing a plurality of rows of cells, each row of cells being provided by:
- (a) providing a plurality of logic cells each having a conductive trace positioned at the predetermined distance relative to the border of the logic cell and laid out along a predetermined direction, the logic cells being laid out abutting each other such that the conductive traces form a power rail along a length of the logic cells;
- and
- (b) providing a switch cell comprising:
- a first conductive trace abutting the power rail;
- a second conductive trace spatically separated from each other;
- and
- a transistor providing a selectably enabled conduction path between the first conductive trace and the second conductive trace.
An integrated circuit comprising a plurality of tapless logic cells power gated by a switch cell.
Dependencies are inferred from the claim text.