Method and system for detailed placement of layout objects in a standard-cell layout design

#1. Field of the Invention

#This invention relates generally to standard-cell layout designs, and more particularly, to a dynamic system and method for adjustment of the placement of layout objects, such as the cells and etch dummies used with standard-cell layout designs.

#2. Description of the Related Art

#So that the above-recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to various embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

#FIG. 1 is a schematic diagram illustrating exemplary elements of a standard-cell layout.

#FIG. 2 is a schematic diagram illustrating the interaction between the polysilicon shapes of the horizontally adjacent cells in a standard-cell layout.

#Various embodiments of the present invention relate to a method and system for detailed placement of layout objects in a standard-cell layout design. A standard-cell layout generated in accordance with various embodiments of the present invention can be used to prepare a photolithography mask that offers improved lithographic characteristics. The lithographic mask can then be used to manufacture an integrated circuit. Layout objects are design objects that need to be positioned in a standard-cell layout design according to specific rules. Layout objects include traditional design objects such as cells. Typically, placement of a cell is chosen by a physical design tool. Exemplary physical design tools include Astro™ from Synopsys and SOC Encounter™ from Cadence. Each cell can further include a plurality of polysilicon shapes and their active-layer shapes. Each of the plurality of polysilicon shapes can include a plurality of gate polysilicon shapes (that is to say, transistor gates) and field polysilicon shapes. Layout objects can also include etch dummies. Etch dummies are added into the standard-cell layout design to reduce the CD skew between the photo and etch processes. Typically, placement of etch dummies is chosen by Resolution Enhancement Technique (RET) tools. Exemplary RET tools include Calibre™ from Mentor Graphics and Proteus™ from Synopsys. Traditionally, etch dummies are placed after the placement of cells. Further, sub-resolution assist features (SRAFs) are also inserted in the standard-cell layout, usually after the placement of etch dummies. SRAFs enhance the printability of isolated patterns onto the wafer. The placement of SRAFs in the standard-cell layout involves possible spacing constraints. Incorrect placement of SRAFs can result in the occurrence of forbidden pitches in the standard-cell layout, as well as unwanted printing of SRAFs on the wafer. Forbidden pitches are those pitches for which the process window of Critical Dimension (CD) is too small.

#Inserting etch dummies with SRAFs necessitates additional spacing constraints. Examples of additional spacing constraints include spacing between active-layer shapes, between polysilicon shapes, and between polysilicon shapes and etch dummies. These additional spacing constraints can be different for the SRAFs and etch dummies.

#FIG. 1 is a schematic diagram illustrating exemplary elements of a standard-cell layout. The standard-cell layout includes a plurality of layout objects and sub-resolution assist features (SRAFs). The plurality of layout objects and SRAFs are placed in the same plane as shown in FIG. 1. Examples of layout objects include, but are not limited to, cells and etch dummies. In an embodiment of the present invention, the cells are arranged in a plurality of rows in the standard-cell layout. The exemplary standard-cell layout shown in FIG. 1 includes a cell 102, a cell 104, an etch dummy 106, an SRAF 108, and an SRAF 110. It will be apparent to those skilled in the art that the standard-cell layout can also include other similar components, as shown in FIG. 1. Cells in a standard-cell layout can include polysilicon and active-layer shapes. Polysilicon shapes further include gate polysilicon shapes (polysilicon over active-layer shape) and field polysilicon shapes or wiring polysilicon shapes. For example, as shown in FIG. 1, cell 102 includes a gate polysilicon shape 112, a field polysilicon shape 114, an active-layer shape 116, and other polysilicon and active-layer shapes. Similarly, cell 104 includes a gate polysilicon shape 118, a field polysilicon shape 120, an active-layer shape 122, and other polysilicon shapes and active-layer shapes.