Hierarchical Signal Integrity Analysis Using Interface Logic Models

A method of generating a model for performing a top-level analysis of a block, the method comprising:

• generating an interface logic module (ILM), the ILM including:
• cells in a timing path that starts at an input port and ends at an output port;
• cells in a timing path that starts at an input port and ends at an edge-triggered register;
• and
• cells in a timing path that starts at an edge-triggered register and ends at an output port;
• and
• any clock tree driving an edge-triggered registers forming part of the interface logic;
• and
• adding any internal net of the block necessary for crosstalk analysis to the ILM, wherein at least one necessary internal net is cross-coupled to an external net of the block and at least one other necessary internal net is cross-coupled to an internal net of the block.

An enhanced interface logic model (ILM) that facilitates accurate signal integrity (SI) analysis of an integrated circuit, the enhanced ILM comprising:

• interface logic of the block, wherein the interface logic includes:
• cells in a timing path that starts at an input port and ends at an output port;
• cells in a timing path that starts at an input port and ends at an edge-triggered register;
• and
• cells in a timing path that starts at an edge-triggered register and ends at an output port;
• and
• any clock tree driving an edge-triggered register forming part of the interface logic;
• an internal component of the block, wherein the internal component includes any internal net cross-coupled to an interface net that forms part of the interface logic, wherein the internal component further includes any internal net cross-coupled to an external net of the block, and wherein the internal component further includes a driver cell associated with the internal net and a load cell associated with the internal net.