Method and apparatus for verifying logic circuit

A logic circuit verification method, comprising:

• verifying functional, timing, and analog characteristics of each node of a logic circuit using waveforms resulting from a simulation of each node of the logic circuit and representations of ideal operations of each node of the logic circuit.

An apparatus for verifying a logic circuit, configured to verify a logic circuit design by comparing waveform characteristics of each node of the logic circuit design with ideal operations of corresponding nodes of a logic circuit design.

An apparatus for verifying a logic circuit design, comprising:

• a wave file generation stage configured to generate a source file representing the logic circuit design and to generate a wave file from the source file, the wave file comprising waveforms corresponding to nodes of the logic circuit design;
• and
• a logic circuit verification stage configured to verify the logic circuit design by comparing the waveforms corresponding to each of the nodes of the logic circuit design with a design reference file representing an ideal operation of each of the nodes of the logic circuit design.