An automatic design system of a semiconductor integrated circuit, comprising:
- a relieving unit configured to increase an interval between a plurality of wiring patterns provided on a chip region to relive a density of the wiring patterns, based on first reference information including a criterion about a restriction of wiring length and second reference information including a criterion for a reduction of defect;
- a chip verifying unit configured to verify a circuit characteristic for the result of the relief;
- and
- a thickening unit configured to perform a first thickening process to thicken the wiring pattern by using a first design rule having a first correction value for thickening the wiring pattern and a second thickening process to thicken the wiring pattern having been thickened in the first thickening process by using a second design rule having a second correction value higher than the first correction value.