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US 2007/0168893 A1Published application
System and method for generating a plurality of models at different levels of abstraction from a single master model
AssigneeCadence Design Systems, Inc.
InventorsYosinori Watanabe, Luciano Lavagno, Alex Kondratyev
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Abstract
A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.
Claims18
A method of producing models of a design of an integrated circuit, the method comprising:
- providing a master model of a design of an integrated circuit;
- and
- translating the master model to at least first and second models functionally equivalent to the master model and at different levels of abstraction from each other and wherein each of the first and second models includes timing information of the design accurate for its respective level of abstraction.
A computer system comprising:
- a CPU;
- a storage;
- and
- a bus coupling the CPU to the storage;
- wherein the storage stores code for execution by the CPU, the code performing:
- providing a master model of a design of an integrated circuit;
- and
- translating the master model to at least first and second models functionally equivalent to the master model and at different levels of abstraction from each other and wherein each of the first and second models includes timing information of the design accurate for its respective level of abstraction.
5 more elements
Dependencies are inferred from the claim text.