Connection verification apparatus for verifying interconnection between multiple logic blocks
AssigneeRenesas Technology Corp.
InventorTakeshi Hashizume
Life of this patent
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Abstract
A connection verification apparatus verifies interconnection between a plurality of logic blocks constituting a semiconductor integrated circuit or the like. It includes a connection verification section for verifying interconnection between a first logic block and a second logic block by comparing a signal level of an output terminal of the first logic block with a signal level of an input terminal of the second logic block connected to the output terminal of the first logic block. The connection verification apparatus can verify the interconnection between the two logic blocks without verifying the logic processing to the two logic blocks.
Claims13
A connection verification method comprising the steps of:
- receiving a signal level from an output terminal of a first logic block;
- receiving a signal level from an input terminal of a second logic block connected to the output terminal of said first logic block, wherein said first and second logic blocks constitute a semiconductor integrated circuit;
- and
- verifying interconnection between said first logic block and said second logic block by comparing the signal level supplied from said first input section with the signal level supplied from said second input section.
A connection verification method comprising the steps of:
- generating a test signal for connection verification, and supplying the test signal to an output terminal of a first logic block;
- receiving a signal level from an input terminal of a second logic block connected to the output terminal of said first logic block, wherein said first and second logic blocks constitute a semiconductor integrated circuit;
- and
- verifying interconnection between said first logic block and said second logic block by comparing a signal level of the test signal generated at said generating step with the signal level supplied at said receiving step.
Dependencies are inferred from the claim text.