Error-detection flip-flop
AssigneeIntel Corporation
InventorsJames Tschanz, Subhasish Mitra, Vivek De
Life of this patent
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Abstract
An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
Claims20
An error-detection circuit, comprising:
- a master-slave flip-flop comprising:
- a master latch driven by a clock, the master latch to receive a first signal and to generate a second signal when the clock is in a first phase;
- and
- a slave latch driven by the clock, the slave latch to receive the second signal and to generate a third signal when the clock is in a second phase;
- and
- a gate to receive the first signal and the second signal, where in the gate is to generate an error signal when the first signal is different from the second signal.
A method comprising:
- receiving a signal into an input of a master latch of a master-slave flip-flop, wherein the signal is received during a first phase of a clock;
- receiving the signal into a slave latch from the master latch;
- identifying a new signal on the input after the clock transitions from the first phase to a second phase;
- and
- generating an error.
An system, comprising:
- a microprocessor comprising an error-detection circuit, the error-detection circuit comprising:
- a master latch driven by a clock, the master latch to receive a first signal and to generate a second signal when the clock is in a first phase;
- and
- a slave latch driven by the clock, the slave latch to receive the second signal and to generate a third signal when the clock is in a second phase;
- and
- a gate to receive the first signal and the second signal, where in the gate is to generate an error signal when the first signal is different from the second signal;
- and
- a battery to supply power to the system.
Dependencies are inferred from the claim text.