Repair bits for a low voltage cache
AssigneeIntel Corporation
InventorsMorgan Dempsey, Jose Maiz
Life of this patent
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Abstract
A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.
Claims37
An apparatus comprising:
- a cache having a plurality of words logically viewable in a plurality of columns;
- a repair cache having a plurality of repair ways, each of the plurality of repair ways associated with one of the plurality of columns;
- a repair module to repair a first bit with a repair bit in a first way of the plurality of repair ways associated with a first column including the first bit.
An apparatus comprising:
- a memory array logically organized into a M rows and N columns;
- a repair array having N replacement bits, each one of the N replacement bits being directly mapped to one of the N columns;
- and
- a module to target a first bit in a first column of the N columns to repair and repair the first bit with a replacement bit of the N replacement bits directly mapped to the first column, upon an access to a row including the first bit.
A system comprising:
- a microprocessor including
- a cache having a plurality of lines, wherein the cache is logically viewable in a plurality of columns;
- a repair module to
- associate a repair bit with each one of the plurality of columns,
- determine a first bit in a first column of the plurality of columns to repair, and
- repair the first bit with the repair bit associated with the first column, upon an access to a line including the first bit;
- a system memory including a plurality of elements coupled to the microprocessor,
- wherein the cache is to store local copies of the contents of the plurality elements.
A method comprising:
- receiving a request to access a cache, the request referencing a first cache line;
- determining if the first cache line includes a first cache location to be repaired;
- and
- repairing the first cache location from a repair cache location associated with the first cache location, upon fulfilling the request to access the cache, if the first cache line includes the first cache location to be repaired.
A method comprising:
- determining an optimal configuration of a plurality of bits in a cache to be repaired with a repair cache, the repair cache including a repair bit directly mapped to each logical vertical stripe of the cache;
- and
- repairing a first bit of the plurality of bits in the cache determined to be repaired with a repair bit directly mapped to a logical vertical stripe including the first bit, upon an access to the cache referencing a word of the cache including the first bit.
Dependencies are inferred from the claim text.