Start/stop circuit for performance counter
AssigneeHewlett-Packard Development Company, L.P.
InventorRichard Adkisson
Life of this patent
Estimating the term…
Abstract
A circuit for tracking a number of clock cycles between occurrences of an event of interest is described. The circuit comprises logic for asserting a run signal responsive to a first occurrence of the event of interest; logic for deasserting the run signal responsive to a second occurrence of the event of interest; and logic for incrementing a count value on each clock cycle while the run signal is asserted.
Claims30
A circuit for tracking a number of clock cycles between occurrences of an event of interest, the circuit comprising:
- logic for asserting a run signal responsive to a first occurrence of the event of interest;
- logic for deasserting the run signal responsive to a second occurrence of the event of interest;
- and
- logic for incrementing a count value on each clock cycle while the run signal is asserted.
A circuit for tracking a number of clock cycles between occurrences of an event of interest, the circuit comprising:
- means for asserting a run signal responsive to a first occurrence of the event of interest;
- means for deasserting the run signal responsive to a second occurrence of the event of interest;
- and
- means for incrementing a count value on each clock cycle while the run signal is asserted.
A method of tracking a number of clock cycles between occurrences of an event of interest, the method comprising:
- asserting a run signal responsive to a first occurrence of the event of interest;
- deasserting the run signal responsive to a second occurrence of the event of interest;
- and
- incrementing a count value on each clock cycle while the run signal is asserted.
Dependencies are inferred from the claim text.