Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in pattern generation program product
AssigneeNEC Electronics Corporation
InventorEiji HARADA
Life of this patent
Estimating the term…
Abstract
A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being configured to an output signal of the scan chain determined according to an output of the circuit under test back to the scan chain.
Claims14
A burn-in test circuit comprising:
- a scan chain formed by a plurality of scan flip-flips connected in series;
- a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal;
- and
- a scan chain loop circuit being configured to feed an output signal of the scan chain back to the scan chain, the output signal of the scan chain being determined according to an output of the circuit under test.
A method for burn-in test for an integrated circuit having a scan chain including a plurality of scan flip-flops connected in series, and a circuit under test that lies between the plurality of scan flip-flops, the method comprising:
- feeding an output signal from the scan chain determined according to an output from the circuit under test back to the scan chain;
- taking the fed back signal in the plurality of scan flip-flops by a scan shift operation;
- and inputting the output signal from one of the plurality of scan flip-flops to the circuit under test as an activation signal.
Dependencies are inferred from the claim text.