US 2007/0168803 A1 · Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Abstract

A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

Claims30

Dependent claims

1-39. (canceled)

An apparatus for inserting a DFD (design-for-debug) circuitry in an integrated circuit to debug or diagnose functional cores each having a selected fault type and a system clock;

said apparatus comprising:
(a) a DFD selector for indicating which said functional cores and said selected fault types will be debugged or diagnosed simultaneously;
(b) a plurality of break registers in each said functional core which are stitched together for storing predetermined break conditions during diagnosis;
(c) a step counter in each said functional core for storing a predetermined number of clock cycles during diagnosis;
(d) a scan connector for connecting multiple scan chains in said functional cores to a boundary-scan chain in said integrated circuit;
(e) a RESET control circuitry that resets the contents of said functional cores when a reset control signal is set to logic value 1;
(f) a BREAK control circuitry in a functional clock controller that accepts a break condition signal from a said functional core to stop said system clock immediately when a break control signal is set to logic value 1 and a said predetermined break condition is met;
(g) a RUN control circuitry in said functional clock controller that allows said system clocks to run forever when a run control signal is set to logic value 1;
(h) a STEP control circuitry in said functional clock controller that accepts a step limit signal from a said functional core to stop said system clock immediately when a step control signal is set to logic value 1 and said system clock has run for an additional, said predetermined number of clock cycles.
(i) a STOP control circuitry in said functional clock controller that stops said system clocks when a stop control signal is set to logic value 1;
and
(j) a multiplexer for connecting said DFD selector and said scan connector to a TAP (test access port) controller in said integrated circuit.

9 more elements

A method for debugging or diagnosing a plurality of functional cores, each having a selected fault type and a system clock, with an embedded DFD (design-for-debug) circuitry in an integrated circuit;

said method comprising:
(a) issuing a DBG_FUNCTION command for generating a functional debug mode to control said DFD circuitry in said functional cores;
(b) issuing a SELECT command for shifting in selected functional cores and said selected fault types to be debugged or diagnosed to the DFD selector of said DFD circuitry in said functional cores;
(c) issuing a RESET command for generating a reset control signal to control said DFD circuitry in said functional cores;
(d) issuing one or more BREAK commands for shifting in predetermined break conditions to stop said system clocks in said functional cores;
(e) issuing a RUN command for generating a run control signal to control said DFD circuitry in said functional cores;
(f) issuing a first SHIFT command or a first plurality of SHIFT_CHAIN commands for shifting data into and out of all said scan cells within selected scan chains in said functional cores for diagnosis;
(g) issuing a STEP command for shifting in a predetermined number of clock cycles to a said functional core and running said system clock for said predetermined number of clock cycles in said functional cores;
(h) issuing a second SHIFT command or a second plurality of SHIFT_CHAIN commands for shifting data into and out of all said scan cells within said selected scan chains in said functional cores for diagnosis;
(i) repeating selected steps of (d)-(h) in any selected order at any time until functional diagnosis is done;
and
(j) issuing a STOP command for generating a stop control signal to control said DFD circuitry in said functional cores.

9 more elements

A method for testing, debugging, or diagnosing scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores in an integrated circuit, each core having a selected fault type and each core type comprising a DFD (design-for-debug) circuitry;

said method comprising:
(a) issuing a RUN_SCAN command for generating a scan test mode to control said DFD circuitry in said scan cores;
(b) issuing a RUN_MBIST command for generating a MBIST test mode to control said DFD circuitry in said memory BIST cores;
(c) issuing a RUN_LBIST command for generating a LBIST test mode to control said DFD circuitry in said logic BIST cores;
(d) issuing a DBG_SCAN command for generating a scan debug mode to control said DFD circuitry in said scan cores;
(e) issuing a DBG_MBIST command for generating a MBIST debug mode to control said DFD circuitry in said memory BIST cores;
(f) issuing a DBG_LBIST command for generating a LBIST debug mode to control said DFD circuitry in said logic BIST cores;
(g) issuing a DBG_FUNCTION command for generating a functional debug mode to control said DFD circuitry in said functional cores;
(h) issuing a SELECT command for shifting in selected cores and said selected fault types to be debugged or diagnosed to the DFD selector of said DFD circuitry in said scan cores, said memory BIST cores, said logic BIST cores, or said functional cores;
(i) issuing a SHIFT command for shifting data into and out of selected scan cells in said scan cores, said memory BIST cores, said logic BIST cores, or said functional cores;
(j) issuing a SHIFT_CHAIN command for shifting data into and out of all scan cells within selected scan chains in said scan cores, said logic BIST cores, or said functional cores;
(k) issuing a CAPTURE command for capturing results into all said scan cells in said scan cores or said memory BIST cores;
(l) issuing a SKIP command for generating a skip control signal to control said DFD circuitry in said memory BIST cores;
(m) issuing a RESET command for generating a reset control signal to control said DFD circuitry in said functional cores;
(n) issuing a BREAK command for generating a break control signal to control said DFD circuitry in said functional cores;
(o) issuing a RUN command for generating a run control signal to control said DFD circuitry in said memory BIST cores, said logic BIST cores, or said functional cores;
(p) issuing a STEP command for generating a step control signal to control said DFD circuitry in said functional cores;
(q) issuing a STOP command for generating a stop control signal to control said DFD circuitry in said scan cores, said memory BIST cores, said logic BIST cores, or said functional cores;
and
(r) repeating selected steps of (a)-(q) in any predetermined order until testing, debugging, or diagnosis of said integrated circuit is done.

17 more elements

Dependencies are inferred from the claim text.

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Life of this patent

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Life of this patent

Abstract

Claims30